Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Pin assignments and reset states
Freescale Semiconductor12
FlexCAN 1
CAN1_TX PB0 UART9_TXD I2C1_SCL — I/O EVDD ssr — D14
CAN1_RX PC7 UART9_RXD I2C1_SDA — I/O EVDD ssr — D15
SDRAM controller
SD_A14 — — — —
O SDVDD st_dec
ap
— P6
SD_A[13:0] — — — — O SDVDD st_dec
ap
P3, M1, M3,
L2, L1, N4,
M2, P2, L3,
L4, N1, N2,
K1, N3
R4, R1, R3,
N4, P3, T4,
R2, T2, N3,
P5, P4, N5,
P2, T3
SD_BA[2:0] — — — — O SDVDD st_dec
ap
M6, J4, P4 P7, N6, R5
SD_CAS —— ——O SDVDD st_dec
ap
K4 N8
SD_CKE — — — — O SDVDD st_dec
ap
N6 R7
SD_CLK — — — — O SDVDD st_ck P6 T5
SD_CLK —— ——O SDVDD st_ck P7 T6
SD_CS —— ——O SDVDD st_dec
ap
M5 N7
SD_D[7:0] — — — — I/O SDVDD st_odt P11, M10,
N10, M9,
P10, M8,
N8, M7
T12, R11,
T11, R10,
N9, T10,
P9, R9
SD_DM — — — — O SDVDD st_odt N7 T7
SD_DQS — — — — I/O SDVDD st_dqs P8 T8
SD_DQS —— ——I/O SDVDD st_dqs P9 T9
SD_ODT — — — — O SDVDD st_dec
ap
P5 P8
SD_RAS —— ——O SDVDD st_dec
ap
M4 R6
SD_WE —— ——O SDVDD st_dec
ap
N5 R8
SD_VREF — — — — — SDVDD st_vref N9 P10
SD_VTT — — — — — SDVDD st_vtt L8 N10
Table 5. MCF5441x Signal information and muxing (continued)
Signal name GPIO Alternate 1 Alternate 2
Pullup (U)
1
Pulldown (D)
Direction
2
Voltage d omain
Pad type
3
196 MAPBGA
256 MAPBGA
