Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Pin assignments and reset states
Freescale Semiconductor14
DSPI0_PCS0/SS
PD7 I2C3_SDA SDHC_DAT3 — I/O EVDD msr J1 K2
DSPI0_SCK/
SBF_CK
PD6 I2C3_SCL SDHC_CLK — I/O EVDD msr J3 L2
DSPI0_SIN/
SBF_DI
PD5 UART3_RXD SDHC_CMD U
14
I EVDD msr K2 L3
DSPI0_SOUT/
SBF_DO
PD4 UART3_TXD SDHC_DAT0 — O EVDD msr J2 K1
One wire
OW_DAT
RGPIO0/PD3 DACK0 — — I/O EVDD ssr M11 N11
DMA timers
T3IN/PWM_EXTA3 RGPIO1/PD2 T3OUT USBO_VBUS_EN/
ULPI_DIR
15
— IEVDDmsr G13 G13
T2IN/PWM_EXTA2 RGPIO2/PD1 T2OUT SDHC_DAT2 — I EVDD msr J12 H14
T1IN/PWM_EXTA1 RGPIO3/PD0 T1OUT SDHC_DAT1 — IEVDDmsr H13 H13
T0IN/PWM_EXTA0 RGPIO4/PE7 T0OUT USBO_VBUS_OC/
ULPI_NXT
16
—
17
I EVDD msr J13 H15
UART 2
UART2_CTS
RGPIO14/PE6 UART6_TXD SSI1_BCLK — IEVDDmsr — M4
UART2_RTS RGPIO15/PE5 UART6_RXD SSI1_FS — OEVDDmsr — M3
UART2_RXD PE4 PWM_A3 SSI1_RXD — IEVDDmsr — P1
UART2_TXD PE3 PWM_B3 SSI1_TXD — I/O
18
EVDD msr — N2
UART 1
UART1_CTS
RGPIO7/PE2 UART5_TXD DSPI3_SCK — IEVDDmsr D12 C10
UART1_RTS RGPIO8/PE1 UART5_RXD DSPI3_PCS0 — OEVDDmsr D11 D10
UART1_RXD PE0 I2C5_SDA DSPI3_SIN — I EVDD msr B10 C9
UART1_TXD PF7 I2C5_SCL DSPI3_SOUT — I/O
18
EVDD msr C10 D9
UART 0
UART0_CTS
RGPIO5/PF6 UART4_TXD DSPI2_SCK — IEVDDmsr E12 E13
UART0_RTS RGPIO6/PF5 UART4_RXD DSPI2_PCS0 — OEVDDmsr C12 B11
UART0_RXD PF4 I2C4_SDA DSPI2_SIN — IEVDDmsr C11 B10
UART0_TXD PF3 I2C4_SCL DSPI2_SOUT — I/O
18
EVDD msr B11 D11
Table 5. MCF5441x Signal information and muxing (continued)
Signal name GPIO Alternate 1 Alternate 2
Pullup (U)
1
Pulldown (D)
Direction
2
Voltage d omain
Pad type
3
196 MAPBGA
256 MAPBGA