Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Pin assignments and reset states
Freescale Semiconductor16
MII0_RXCLK PK3 RMII1_RXER ULPI_DATA6 — I
EVDD fsr — M14
MII0_TXD[3:2] PK[2:1] RMII1_TXD[1:0] ULPI_DATA[3:2] — O EVDD fsr — T13, N12
MII0_TXCLK PK0 RMII1_TXEN ULPI_DATA7 D
21
I EVDD fsr — T14
BDM/JTAG
ALLPST
22
PH2 — — — OEVDD fsr K12 —
DDATA[3:2] PH[1:0] — — — O EVDD fsr — L15, M13
DDATA[1:0] PI[7:6] — — — O EVDD fsr — M15, L14
PST[3:0] PI[5:2] — — — O EVDD fsr — J13, J16,
J15, J14
JTAG_EN — — — D IEVDDmsr N11 N15
PSTCLK — TCLK
23
——IEVDDfsr L14 M16
DSI — TDI
23
—UIEVDDmsr L10 L13
DSO — TDO
23
——O EVDD msr L13 K14
BKPT —TMS
23
—UIEVDDmsr K13 K16
DSCLK — TRST
23
—UI EVDD msr L9 K13
Test
(this signal must be grounded)
TEST — — — D
IEVDDssr K10 R16
Power supplies
IVDD — — — — — — —
D9, D10,
E9, E10, F9,
F10, F12
E9–E11,
F9–F11
EVDD — — — — — — — F4–F7, G6,
G7, H6, H7,
J5, J6
H8, J7–J10,
K6–K11, L6
FB_VDD — — — — — — — D5–D7,
E4–E7
E5–E7, F5,
F6, G5
SD_VDD — — — — — — — K7–K9,
L5–L7
M7–M12
VDD_OSC_A_PLL — — — — — — vddint F14 F15
VSS_OSC_A_PLL — — — — — — vddint F13 F16
VDD_USBO — — — — — — vdde F11 G12
VDD_USBH — — — — — — vdde — H12
VDDA_ADC — — — ——— — — H4
Table 5. MCF5441x Signal information and muxing (continued)
Signal name GPIO Alternate 1 Alternate 2
Pullup (U)
1
Pulldown (D)
Direction
2
Voltage d omain
Pad type
3
196 MAPBGA
256 MAPBGA