Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor2
Table of Contents
1 MCF5441x family comparison . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 Supply voltage sequencing . . . . . . . . . . . . . . . . . . . . . . .7
2.2.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . .8
2.2.2 Power-down sequence . . . . . . . . . . . . . . . . . . . .8
2.3 Power consumption specifications . . . . . . . . . . . . . . . . .8
3 Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .9
3.1 Signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .20
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21
4.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .22
4.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.4 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .23
4.6 Output pad loading and slew rate . . . . . . . . . . . . . . . . .25
4.7 DDR pad drive strengths. . . . . . . . . . . . . . . . . . . . . . . .26
4.8 Oscillator and PLL electrical characteristics . . . . . . . . .26
4.9 Reset timing specifications . . . . . . . . . . . . . . . . . . . . . .28
4.10 FlexBus timing specifications . . . . . . . . . . . . . . . . . . . .28
4.11 NAND flash controller (NFC) timing specifications . . . .30
4.12 DDR SDRAM controller timing specifications . . . . . . . .33
4.13 USB transceiver timing specifications . . . . . . . . . . . . . .35
4.14 ULPI timing specifications. . . . . . . . . . . . . . . . . . . . . . .35
4.15 eSDHC timing specifications. . . . . . . . . . . . . . . . . . . . .36
4.15.1 eSDHC timing specifications . . . . . . . . . . . . . . .37
4.15.2 eSDHC electrical DC characteristics . . . . . . . . 38
4.16 SIM timing specifications . . . . . . . . . . . . . . . . . . . . . . . 38
4.16.1 General timing requirements . . . . . . . . . . . . . . 39
4.16.2 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . 39
4.16.3 Power-down sequence . . . . . . . . . . . . . . . . . . . 40
4.17 SSI timing specifications . . . . . . . . . . . . . . . . . . . . . . . 41
4.18 12-bit ADC specifications . . . . . . . . . . . . . . . . . . . . . . 43
4.19 12-bit DAC timing specifications . . . . . . . . . . . . . . . . . 44
4.20 mcPWM timing specifications . . . . . . . . . . . . . . . . . . . 45
4.21 I
2
C timing specifications . . . . . . . . . . . . . . . . . . . . . . . 45
4.22 Ethernet assembly timing specifications . . . . . . . . . . . 46
4.22.1 Receive signal timing specifications. . . . . . . . . 47
4.22.2 Transmit signal timing specifications . . . . . . . . 47
4.22.3 Asynchronous input signal timing
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.22.4 MDIO serial management timing
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.23 32-bit timer module timing specifications. . . . . . . . . . . 49
4.24 DSPI timing specifications . . . . . . . . . . . . . . . . . . . . . . 49
4.25 SBF timing specifications . . . . . . . . . . . . . . . . . . . . . . 52
4.26 1-Wire timing specifications. . . . . . . . . . . . . . . . . . . . . 53
4.27 General purpose I/O timing specifications. . . . . . . . . . 53
4.28 Rapid general purpose I/O timing specifications . . . . . 53
4.29 JTAG and boundary scan timing specifications . . . . . . 54
4.30 Debug AC timing specifications . . . . . . . . . . . . . . . . . . 56
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6 Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
