Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Pin assignments and reset states
Freescale Semiconductor20
3.3 Pinout—256 MAPBGA
The pinout for the MCF54415, MCF54416, MCF54417, and MCF54418 packages are shown below.
12345678910111213141516
A
VSS
FB_
AD3
FB_
AD13
FB_
AD14
FB_
AD16
FB_
AD20
FB_
AD22
FB_
AD26
FB_
AD29
SDHC_
CLK
SIM0_
CLK
SSI0_
MCLK
SSI0_
BCLK
USBO_
DM
USBH_
DM
VSS A
B
FB_
CS4
FB_
AD2
FB_
AD8
FB_
AD11
FB_
AD15
FB_
AD19
FB_
AD24
FB_
AD28
FB_
AD31
UART0_
RXD
UART0_
RTS
SDHC_
DAT0
SDHC_
DAT3
USBO_
DP
USBH_
DP
RTC_
EXTAL
B
C
FB_BE/
BWE3
FB_
AD1
FB_
AD7
FB_
AD9
FB_
AD10
FB_
AD17
FB_
AD23
FB_
AD30
UART1_
RXD
UART1_
CTS
SDHC_
CMD
SSI0_
RXD
SSI0_
TXD
SIM0_
PD
SIM0_
RST
RTC_
XTAL
C
D
FB_BE/
BWE1
FB_
ALE
FB_
AD5
FB_
AD12
FB_
AD18
FB_
AD21
FB_
AD25
FB_
AD27
UART1_
TXD
UART1_
RTS
UART0_
TXD
SDHC_
DAT1
SIM0_
VEN
CAN1_
TX
CAN1_
RX
VSS D
E
FB_
CS1
FB_
BE/BW
E2
FB_
AD4
FB_
AD6
FB_
VDD
FB_
VDD
FB_
VDD
VSS
IVDD IVDD IVDD
SIM0_
XMT
UART0
_CTS
SDHC_
DAT2
SSI0_
FS
VSTBY_
RTC
E
F
FB_
OE
FB_
CS5
FB_
AD0
FB_BE/
BWE0
FB_
VDD
FB_
VDD
VSS VSS
IVDD IVDD IVDD
IRQ7
IRQ1 IRQ4
VDD_
OSC_A
_PLL
VSS_
OSC_A
_PLL
F
G
FB_
CLK
FB_
R/W
FB_
CS0
ADC_
IN4
FB_
VDD
VSS VSS VSS VSS VSS VSS
VDD_
USBO
T3IN
I2C0_
SDA
I2C0_
SCL
EXTAL
G
H
ADC_
IN0
ADC_
IN6
FB_
TA
AVDD_
ADC
AVSS_
ADC
VSS VSS EVDD VSS VSS VSS
VDD_
USBH
T1IN T2IN T0IN XTAL
H
J
ADC_
IN1
ADC_
IN2
ADC_
IN5
VDDA_
DAC_
ADC
VSSA_
DAC_
ADC
VSS EVDD EVDD EVDD EVDD VSS VSS
PST3 PST0 PST1 PST2
J
K
DSPI0_
SOUT
DSPI0_
PCS0
ADC_
IN7
ADC_
IN3
BOOT
MOD1
EVDD EVDD EVDD EVDD EVDD EVDD VSS TRST
TDO
RESET
TMS
K
L
DSPI0_
PCS1
DSPI0_
SCK
DSPI0_
SIN
VSS
BOOT
MOD0
EVDD VSS VSS VSS VSS VSS VSS
TDI DDATA0 DDATA3
RST
OUT
L
M IRQ3
IRQ2
UART2_
RTS
UART2_
CTS
VSS VSS
SD_
VDD
SD_
VDD
SD_
VDD
SD_
VDD
SD_
VDD
SD_
VDD
DDATA2
MII0_
RXCLK
DDATA1 TCLK
M
N IRQ6
UART2_
TXD
SD_A5 SD_A10 SD_A2 SD_BA1
SD_CS
SD_
CAS
SD_D3 SD_VTT
OW_
IO
MII0_
TXD2
MII0_
RXD2
MII0_
RXER
JTAG_
EN
MII0_
MDIO
N
P
UART2_
RXD
SD_A1 SD_A9 SD_A3 SD_A4 SD_A14 SD_BA2
SD_
ODT
SD_D1
SD_
VREF
MII0_
CRS
MII0_
TXEN
MII0_
TXD0
MII0_
RXDV
MII0_
RXD3
MII0_
MDC
P
R
SD_A12 SD_A7 SD_A11 SD_A13 SD_BA0
SD_
RAS
SD_
CKE
SD_WE
SD_D0 SD_D4 SD_D6
MII0_
COL
MII0_
TXD1
MII0_
TXER
MII0_
RXD1
TEST
R
T
VSS
SD_A6 SD_A0 SD_A8
SD_
CLK
SD_
CLK
SD_
DM
SD_
DQS
SD_
DQS
SD_D2 SD_D5 SD_D7
MII0_
TXD3
MII0_
TXCLK
MII0_
RXD0
VSS T
12345678910111213141516
Figure 8. MCF54415, MCF54416, MCF54417, and MCF54418 Pinout (256 MAPBGA)