Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 23
Solving equations 1 and 2 for K gives:
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P
D
(at equilibrium)
for a known T
A
. Using this value of K, the values of P
D
and T
J
can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of T
A
.
4.3 ESD protection
4.4 Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply over voltage is applied to each power supply pin.
• A current injection is applied to each input, output, and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
4.5 DC electrical specifications
Table 8. ESD protection characteristics
1,
2
1
All ESD testing is in conformity with JESD22 Stress Test Qualification.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable specification at room temperature followed by hot temperature,
unless specified otherwise in the device specifications provided in this document.
Characteristics Symbol Value Units
ESD Target for Human Body Model HBM 2000 V
Table 9. Latch-up results
No. Symbol Parameter Conditions Class
1 LU CC Static latch-up class T
A
= 125 °C conforming to JESD 78 II level A
Table 10. Power supply specifications
Characteristic Symbol Pin Name Min Max Units
Internal logic supply voltage, nominal 1.2 V IV
DD
IVDD
1.14 1.32 V
FlexBus supply voltage
Nominal 1.8–3.3 V
FBV
DD
FB_VDD
1.71 3.63
V
SDRAM supply voltage
DDR2 @ 1.8 V
SDV
DD
SD_VDD
1.71 1.98
V
SDRAM input reference voltage SDV
REF
SD_VREF
0.49 x SDV
DD
0.51 x SDV
DD
V
SDRAM termination supply voltage SDV
TT
SD_VTT
SDV
REF
–0.04 SDV
REF
+0.04 V
PLL analog operation voltage range, nominal 3.3 V PV
DD
VDD_OSC_
A_PLL
3.135 3.63 V
KP
D
T
A
273CQ
JMA
P
D
2
+=