Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 25
4.6 Output pad loading and slew rate
The output pins on the MCF5441x devices have programmable slew rates. Table 12 lists the rise/fall time for pins based on the
type of pad used for the signal, the value programmed into the appropriate field of the slew rate control registers, and capacitive
loading. Refer to Table 5 for a list of the external signals to pad connections.
NOTE
To allow the I/O interfaces to run at their maximum frequency, set their respective slew rate
select values to 11.
Weak internal pull-up/pull-down device current
1
I
APU
10 315 A
Selectable weak internal pull-up/pull-down device current
1
I
APU
25 150 A
Input capacitance
2
All input-only pins
All input/output (three-state) pins
C
in
—
—
7
7
pF
Output loading for CMOS pads (EV
DD
and FBV
DD
domains)
Low drive
High drive
C
L
50
200
pF
Output loading for SDRAMC pads (SDV
DD
domain)
Low drive
High drive
C
L
5
50
pF
1
Refer to the signals section for pins having weak internal pull-up devices.
2
This parameter is characterized before qualification rather than 100% tested.
Table 12. Output pad slew rates
Pad type
1
Slew rate select
field value
Drive load
(pF)
Rise/fall time
(ns)
ssr
11
50 2.2
200 6
10
50 22
200 28
01
50 42
200 50
00
50 210
200 220
Table 11. I/O electrical specifications (continued)
Characteristic Symbol Min Max Units