Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor26
4.7 DDR pad drive strengths
The DDR pins on the MCF5441x devices have programmable drive strengths. Table 13 lists the drive strengths for pins based
on the value programmed into the appropriate field of the drive strength control register. Refer to Table 5 for a list of the external
signals to pad connections.
NOTE
For a single device drive, this setting should be 00 to enable Half Strength mode. High
strength is intended for multiple device drives (DIMM).
msr
11
50 1.2
200 6
10
50 9
200 14
01
50 17
200 23
00
50 110
200 120
fsr
11
50 1.1
200 2.6
10
50 2.4
200 5
01
50 5
200 8
00
50 16
200 21
1
The ae pads are used for USB communication and are governed by usb.org
specifications. They are not included in this table.
Table 13. DDR pad drive strengths
Pad type
Drive strength select
field value
Drive strength
st 00 Half strength 1.8V DDR2
01 Full strength 1.8V DDR2
10 Reserved
11 Reserved
Table 12. Output pad slew rates (continued)
Pad type
1
Slew rate select
field value
Drive load
(pF)
Rise/fall time
(ns)