Datasheet

Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 27
4.8 Oscillator and PLL electrical characteristics
Reference Figure 9 for crystal circuits.
Table 14. PLL electrical characteristics
Num Characteristic Symbol Min Max Unit
1 PLL Reference Frequency Range
1
Crystal reference
External reference
f
ref_crystal
f
ref_ext
14
1
14
1
50
1
50
1
1
These reference value ranges are for after a PLL predivider (PREDIV), which can be programmed to 1, 2, 4, 8, or 16.
The PREDIV value can be set while booting from serial flash. In parallel reset configuration, the PREDIV value is set to
one. In this mode, if the input frequency results in an out of range reference frequency, boot the processor in limp
mode, set the proper PREDIV and multiplier settings, and switch to PLL mode.
MHz
MHz
2 Core frequency
FB_CLK frequency
2
(MISCCR2[FBHALF] = 0)
2
All internal registers retain data at 0 Hz.
f
sys
f
sys/2
120
60
250
100
MHz
MHz
3 VCO frequency f
vco
240 500 MHz
4 DCC frequency
3
3
Required only for DDR2 memory.
f
DCC
300 500 MHz
5 Crystal start-up time
4, 5
4
This parameter is guaranteed by characterization before qualification rather than 100% tested.
5
Proper PC board layout procedures must be followed to achieve specifications.
t
cst
—10ms
6 EXTAL input high voltage
External and limp modes V
IHEXT
EV
IH
EVDD V
7 EXTAL input low voltage
External and limp modes V
ILEXT
0EV
IL
V
8PLL lock time
4, 6
6
This specification is the PLL lock time only and does not include oscillator start-up time.
t
lpll
—50ms
9 Duty cycle of reference
4
t
dc
–45% +45% %
10 Crystal capacitive load C
L
— From crystal
spec
pF
11 Feedback resistor R
F
10 — M
12 Series resistor R
S
0 200 
13 Discrete load capacitance for XTAL C
L_XTAL
—2 C
L
–
C
S_XTAL
–
C
PCB_XTAL
7
7
C
PCB_EXTAL
and C
PCB_XTAL
are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
pF
14 Discrete load capacitance for EXTAL C
L_EXTAL
—2 C
L
–
C
S_EXTAL
–
C
PCB_EXTAL
7
pF
15 FB_CLK period jitter,
4, 5, 7, 8,
Measured at f
SYS
Max
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL V
DD
, EV
DD
, and V
SS
and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
C
jitter
—
—
10
0.1
% f
sys/3
% f
sys/3