Datasheet

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor28
Figure 9. Typical crystal circuit
4.9 Reset timing specifications
Table 15 lists specifications for the reset timing parameters shown in Figure 10.
Table 15. Reset and configuration override timing
Num Characteristic Min Max Unit
R1
1
1
RESET and configuration override data lines are synchronized internally. Setup and hold times must be met only if
recognition on a particular clock is required.
RESET
valid to FB_CLK (setup) 9 — ns
R2 FB_CLK to RESET
invalid (hold) 1.5 — ns
R3 RESET
valid time
2
2
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously
to the system. Thus, RESET must be held a minimum of 100 ns.
5 — FB_CLK cycles
R4 FB_CLK to RSTOUT
valid — 10 ns
R5 RSTOUT
valid to Configuration Override inputs valid 0 — ns
R6 Configuration Override inputs valid to RSTOUT
invalid (setup) 20 — FB_CLK cycles
R7 Configuration Override inputs invalid after RSTOUT
invalid (hold) 0 — ns
R8 RSTOUT
invalid to Configuration Override inputs High Impedance — 1 FB_CLK cycles
R9 Minimum RSTOUT pulse width 512 — FB_CLK cycles
XOSC
EXTAL XTAL
Crystal or Resonator
R
S
C
2
R
F
C
1
C
L
C
L