Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 29
Figure 10. RESET and configuration override timing
4.10 FlexBus timing specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a
reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the FlexBus output clock
(FB_CLK). All other timing relationships can be derived from these values.
All FlexBus signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load
of 50 pF.
1
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 16. FlexBus timing specifications
Num Characteristic Min Max Unit Notes
Frequency of operation — 62.5 MHz
FB1 Clock period 16 — ns
FB2 Output valid — 6.0 ns
1
1
Specification is valid for all FB_AD[31:0], FB_R/W, FB_ALE, FB_TS, FB_CSn, FB_OE, FB_BE/BWEn,
and FB_TSIZ[1:0].
FB3 Output hold 0.5 — ns
1
FB4 Input setup 5.5 — ns
2
2
Specification is valid for all FB_AD[31:0] and FB_TA.
FB5 Input hold 0 — ns
2
R1
R2
FB_CLK
RESET
RSTOUT
R3
R4
R8
R7R6R5
R4
BOOTMOD[1:0]
R9