Datasheet

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor34
Figure 16. Read data latch timing
4.12 DDR SDRAM controller timing specifications
The following timing numbers must be followed to properly latch or drive data onto the SDRAM memory bus. All timing
numbers are relative to the DQS byte lanes.
Table 18. SDRAM timing specifications
Num Characteristic Symbol Min Max Unit Notes
Frequency of operation 100 250 MHz
DD1 Clock period t
SDCK
4.0 10.0 ns
DD2 Pulse width high t
SDCKH
0.45 0.55 t
SDCK
1
1
Pulse width high plus pulse width low cannot exceed min and max clock period.
DD3 Pulse width low t
SDCKL
0.45 0.55 t
SDCK
3
DD4 Address, SD_CKE, SD_CAS
, SD_RAS,
SD_WE, SD_CS[1:0] — output valid
t
CMV
—0.5 t
SDCK
+ 1 ns
2
2
Command output valid should be 1/2 the memory bus clock (t
SDCK
) plus some minor adjustments for process, temperature,
and voltage variations.
DD5 Address, SD_CKE, SD_CAS, SD_RAS,
SD_WE, SD_CS[1:0] — output hold
t
CMH
0.5  t
SDCK
– 1 — ns
DD6 Write command to first DQS latching transition t
DQSS
—WL+0.2 t
SDCK
ns
DD7 Data and data mask output setup (DQDQS)
relative to DQS (DDR write mode)
t
QS
0.4 — ns
3
4
DD8 Data and data mask output hold (DQSDQ)
relative to DQS (DDR write mode)
t
QH
0.4 — ns
5
DD9 Input data skew relative to DQS (input setup) t
IS
—0.5ns
6
DD10 Input data hold relative to DQS. t
IH
0.375  t
SDCK
—ns
7
NFC_R/B
NF13
NFC_CE
NFC_RE
NFC_IO[15:0]
Data from NF
NF5
NF15
NF16
NF10
NF14
NF17