Datasheet

Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 35
Figure 17. DDR write timing
3
This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be
larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
4
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are
valid for each subsequent DQS edge.
5
This specification relates to the required hold time of DDR memories.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
6
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
7
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
SD_CLK
SD_CSn,SD_WE,
SD_DM
SD_D[7:0]
SD_A[13:0]
SD_RAS
, SD_CAS
CMD
ROW
DD1
DD5
DD4
COL
WD1 WD2 WD3 WD4
DD7
SD_DQS
DD8
DD8
DD7
SD_CLK
DD3
DD2
DD6