Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor36
Figure 18. DDR read timing
4.13 USB transceiver timing specifications
The MCF5441x device is compliant with industry standard USB 2.0 specification.
4.14 ULPI timing specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing
requirements for the ULPI pins are given in Table 19. These timings apply to synchronous mode only. All timings are measured
with respect to the clock as seen at the USB_CLKIN pin on the MCF5441x. The ULPI PHY is the source of the 60MHz clock.
NOTE
The USB controller requires a 60-MHz clock, even if using the on-chip FS/LS transceiver
instead of the ULPI interface. In this case, the 60-MHz clock can be generated by the PLL
or input on the USB_CLKIN pin.
SD_CLK
SD_CS
n,SD_WE,
SD_DQS
SD_D[7:0]
SD_A[13:0]
SD_RAS
, SD_CAS
CMD
ROW
DD1
DD5
DD4
RD1 RD2 RD3 RD4
SD_DQS
DD9
SD_CLK
DD3
DD2
SD_D[7:0]
RD1 RD2 RD3 RD4
DD10
CL=2
CL=2.5
COL
DQS Read
Preamble
DQS Read
Postamble
DQS Read
Preamble
DQS Read
Postamble
CL = 2.5
CL = 2