Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor38
4.15.1 eSDHC timing specifications
Figure 20 depicts the timing of eSDHC, and Table 20 lists the eSDHC timing characteristics.
Figure 20. eSDHC timing
Table 20. eSDHC interface timing specifications
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock frequency (low speed) f
PP
1
1
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
0 400 kHz
Clock frequency (SD/SDIO full speed) f
PP
2
2
In normal data transfer mode for SD/SDIO card, clock frequency can be any value from 0 to 25 MHz.
040MHz
Clock frequency (MMC full speed) f
PP
3
3
In normal data transfer mode for MMC card, clock frequency can be any value from 0 to 20 MHz.
020MHz
Clock frequency (identification mode) f
OD
4
4
In card identification mode, card clock must be 100 kHz– 400 kHz, voltage ranges from 2.7 to 3.6 V.
100 400 kHz
SD2 Clock low time t
WL
7—ns
SD3 Clock high time t
WH
7—ns
SD4 Clock rise time t
TLH
—3ns
SD5 Clock fall time t
THL
—3ns
eSDHC Output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 eSDHC output delay (output valid) t
OD
–5 5 ns
eSDHC Input / card outputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 eSDHC input setup time t
ISU
5—ns
SD8 eSDHC input hold time t
IH
0—ns
SD1
SD3
SD5
SD4
SD7
SDHC_CMD
Output from eSDHC to card
SDHC_DAT[3:0]
SDHC_CMD
Input from card to eSDHC
SDHC_DAT[3:0]
SDHC_CLK
SD2
SD8
SD6