Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
MCF5441x family comparison
Freescale Semiconductor4
1 MCF5441x family comparison
Table 1. MCF5441x family configurations
Module MCF54410 MCF54415 MCF54416 MCF54417 MCF54418
Version 4 ColdFire core with EMAC (enhanced
multiply-accumulate unit) and MMU (memory
management unit)
Cryptography acceleration unit (CAU) — — —
Core (system) and SDRAM clock up to 250 MHz
Peripheral clock
(Core clock 2)
up to 125 MHz
External bus (FlexBus) clock up to 100 MHz
Performance (Dhrystone 2.1 MIPS) up to 385
Static RAM (SRAM) 64 KB
Independent data/instruction cache 8 KB each
USB 2.0 Host controller —
USB 2.0 Host/Device/On-the-Go controller
UTMI+ Low Pin Interface (ULPI) for external
high-speed USB PHY
—
10/100 Mbps Ethernet controller with IEEE 1588
support
12222
Level 2 IEEE 1588-compliant 3-port Ethernet
switch
———
Enhanced Secure Digital host controller (eSDHC)
Smart card/Subscriber Identity Module (SIM) — 2 ports 2 ports 2 ports 2 ports
UARTs 6 10 10 10 10
DSPI 34444
CAN 2.0B controllers 12222
I
2
C 46666
Synchronous serial interface (SSI) 12222
12-bit ADC —
12-bit DAC — 2 2 2 2
32-bit DMA timers 44444
Periodic interrupt timers (PIT) 44444
Motor control PWM timer (mcPWM) — 8 channel 8 channel 8 channel 8 channel
64-channel DMA controller
Real-time clock with 2 KB standby RAM and
battery back-up input
DDR2 SDRAM controller
FlexBus external memory controller