Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor40
4.16.1 General timing requirements
Figure 21 shows the timing of the SIM module, and Table 22 lists the timing parameters.
Figure 21. SIM clock timing diagram
4.16.2 Reset sequence
4.16.2.1 Cards with internal reset
The reset sequence for this kind of SIM card is as follows (see Figure 22):
• After powerup, the clock signal is enabled on SIM_CLK (time T0)
• After 200 clock cycles, RX must be high.
• The card must send a response on RX acknowledging the reset between 400 and 40,000 clock cycles after T0.
Figure 22. Internal-reset card reset sequence
Table 22. SIM timing specification—High Drive strength
Num Description Symbol Min Max Unit
1 SIM clock frequency (SIM_CLK)
1
1
50% duty cycle clock
S
freq
0.01 5 (Some new cards
may reach 10)
MHz
2 SIM_CLK rise time
2
2
With C = 50pF
S
rise
–20ns
3 SIM_CLK fall time
3
3
With C = 50pF
S
fall
–20ns
4 SIM input transition time (RX, SIM_PD) S
trans
–25ns
SIM_CLK
SriseSfall
1/Sfreq
SIM_VEN
SIM_CLK
SIM_RX
2
T0
1
Response
2
1
< 200 clock cycles
< 40,000 clock cycles400 clock cycles <