Datasheet

Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 43
Table 24. SSI timing — master modes
1
1
All timings specified with a capacitive load of 25pF.
Num Description Symbol Min Max Units Notes
S1 SSI_MCLK cycle time t
MCLK
15.15 — ns
2
2
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (f
sys
).
S2 SSI_MCLK pulse width high / low 45% 55% t
MCLK
S3 SSI_BCLK cycle time t
BCLK
80 — ns
3
3
SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (f
sys
).
S4 SSI_BCLK pulse width 45% 55% t
BCLK
S5 SSI_BCLK to SSI_FS output valid — 15 ns
S6 SSI_BCLK to SSI_FS output invalid 0 — ns
S7 SSI_BCLK to SSI_TXD valid — 15 ns
S8 SSI_BCLK to SSI_TXD invalid / high impedance 0 — ns
S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 15 — ns
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns
Table 25. SSI timing — slave modes
1
1
All timings specified with a capacitive load of 25pF.
Num Description Symbol Min Max Units Notes
S11 SSI_BCLK cycle time t
BCLK
80 — ns
S12 SSI_BCLK pulse width high / low 45% 55% t
BCLK
S13 SSI_FS input setup before SSI_BCLK 10 — ns
S14 SSI_FS input hold after SSI_BCLK 2 — ns
S15 SSI_BCLK to SSI_TXD / SSI_FS output valid — 15 ns
S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedance
0— ns
S17 SSI_RXD setup before SSI_BCLK 15 — ns
S18 SSI_RXD hold after SSI_BCLK 2 — ns