Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 45
4.19 12-bit DAC timing specifications
Table 27 shows electrical specifications of DAC.
Differential non-linearity (10% to 90% input signal
range)
3
DNL — ±0.6 — lsb
Monotonicity Guaranteed
Conversion time — — 6 t
ADC
cycles
Sample time — — 1 t
ADC
cycles
ADC power-up time
4
t
ADPU
——13t
ADC
cycles
5
Recovery from auto standby t
REC
—0 6t
ADC
cycles
Input impedance X
IN
—2k—
Input injection current
6
, per pin I
ADI
—— 3 mA
V
REFH
current I
VREFH
—100— nA
Offset voltage internal reference (at the y intercept) V
OFFSET0
—±20— LSB
Offset voltage internal reference (at the 50% FSR point) V
OFFSET50
—±12— LSB
Gain error (transfer path) E
GAIN
—±0.2— %
Spurious free dynamic range SFDR — 57 — dB
Signal-to-noise plus distortion SINAD — 55 — dB
Signal-to-noise ratio SNR — 60 — dB
Effective number of bits ENOB — 9 — Bits
1
All ADC parameter measurements are preliminary pending full characterization.
These measurements were made at V
DD
=3.3V, V
REFH
= 3.3 V, and V
REFL
= ground.
2
INL measured from V
IN
= 0.1V
REFH
to V
IN
= 0.9V
REFH
3
INL measured from V
IN
= 0.1V
REFH
to V
IN
= 0.9V
REFH
4
Includes power-up of ADC and V
REF
5
ADC clock cycles
6
The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC
Table 27. DAC parameters
1
Characteristic Name Min Typical Max Unit
Range of digital input words: 497 to 3599 (0x1F1–0xE0F) LSB — 806 — uV
Monotonicity Guaranteed
Conversion time (high-speed) 1 — — us
Conversion time (low-speed) 2 — — us
Conversion rate (high-speed) — — 1M conv/sec
Conversion rate (low-speed) — — 500K conv/sec
Output swing AVSS + 0.04 — AVDD – 0.04 V
Table 26. ADC parameters
1
(continued)
Characteristic Name Min Typical Max Unit
