Datasheet

MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor46
4.20 mcPWM timing specifications
4.21 I
2
C timing specifications
Table 29 lists specifications for the I
2
C input timing parameters shown in Figure 27.
Table 30 lists specifications for the I
2
C output timing parameters shown in Figure 27.
Integral non-linearity (497 to 3599) INL — — ±8.0 lsb
Differential non-linearity (497 to 3599) DNL — — ±0.5 lsb
Gain error (497 to 3599) E
GAIN
— ±0.26 — %
Effective number of bits ENOB 9 — — bits
DAC power-up time t
DAPU
— — 11 us
Output load resistance R
L
3K — — Ohm
Output load capacitance C
L
— 400 — pF
Power supply ripple rejection PSRR — 60 — dB
1
All measurements were made at V
DD
= 3.3V, V
REFH
= 3.3V, and V
REFL
= ground
Table 28. mcPWM timing
Num Characteristic Min Max Unit
G1 FB_CLK high to output valid — 7 ns
G2 FB_CLK high to output invalid 1 — ns
G3 Input valid to FB_CLK high 3 — ns
G4 FB_CLK high to input invalid 1 — ns
Table 29. I
2
C input timing specifications between SCL and SDA
Num Characteristic Min Max Units
I1 Start condition hold time 2 — 1/f
SYS
I2 Clock low period 8 — 1/f
SYS
I3 I2C_SCL/I2C_SDA rise time (V
IL
= 0.5 V to V
IH
=2.4 V) — 1 ms
I4 Data hold time 0 — ns
I5 I2C_SCL/I2C_SDA fall time (V
IH
= 2.4 V to V
IL
=0.5 V) — 1 ms
I6 Clock high time 4 — 1/f
SYS
I7 Data setup time 0 — ns
I8 Start condition setup time (for repeated start condition only) 2 — 1/f
SYS
I9 Stop condition setup time 2 — 1/f
SYS
Table 27. DAC parameters
1
(continued)
Characteristic Name Min Typical Max Unit