Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 47
Figure 27. I
2
C input/output timings
4.22 Ethernet assembly timing specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
All Ethernet signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load
of 50 pF.
1
Table 30. I
2
C output timing specifications between SCL and SDA
Num Characteristic Min Max Units
I1
1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Ta bl e 3 0. The I
2
C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR. However, the numbers
given in Ta bl e 30 are minimum values.
Start condition hold time 6 — 1/f
SYS
I2
1
Clock low period 10 — 1/f
SYS
I3
2
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
I2C_SCL/I2C_SDA rise time (V
IL
= 0.5 V to V
IH
=2.4 V) — — µs
I4
1
Data hold time 7 — 1/f
SYS
I5
3
3
Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 3 ns
I6
1
Clock high time 10 — 1/f
SYS
I7
1
Data setup time 2 — 1/f
SYS
I8
1
Start condition setup time (for repeated start condition only) 20 — 1/f
SYS
I9
1
Stop condition setup time 10 — 1/f
SYS
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA