Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor48
4.22.1 Receive signal timing specifications
The following timing specs meet the requirements for MII and RMII interfaces for a range of transceiver devices.
Figure 28. MII/RMII receive signal timing diagram
4.22.2 Transmit signal timing specifications
Table 31. Receive signal timing
Num Characteristic
MII mode RMII mode
Unit
Min Max Min Max
— RXCLK frequency — 25 — 50 MHz
E1 RXD[n:0], RXDV, RXER to RXCLK setup
1
1
In MII mode, n = 3; In RMII mode, n = 1
5—4— ns
E2 RXCLK to RXD[n:0], RXDV, RXER hold
1
5—2— ns
E3 RXCLK pulse width high 35% 65% 35% 65% RXCLK period
E4 RXCLK pulse width low 35% 65% 35% 65% RXCLK period
Table 32. Transmit signal timing
Num Characteristic
MII mode RMII mode
Unit
Min Max Min Max
— TXCLK frequency — 25 — 50 MHz
E5 TXCLK to TXD[n:0], TXEN, TXER invalid
1
1
In MII mode, n = 3; In RMII mode, n = 1
4—5— ns
E6 TXCLK to TXD[n:0], TXEN, TXER valid
1
— 25 — 14 ns
E7 TXCLK pulse width high 35% 65% 35% 65% t
TXCLK
E8 TXCLK pulse width low 35% 65% 35% 65% t
TXCLK
Valid Data
RXCLK (MII) / EXTAL (RMII)
RXD[n:0]
RXDV,
RXER
E3
E4
E1
E2