Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 49
Figure 29. MII/RMII transmit signal timing diagram
4.22.3 Asynchronous input signal timing specifications
Figure 30. MII/RMII async inputs timing diagram
4.22.4 MDIO serial management timing specifications
Table 33. MII/RMII transmit signal timing
Num Characteristic Min Max Unit
E9 CRS, COL minimum pulse width 1.5 — TXCLK period
Table 34. MDIO serial management channel signal timing
Num Characteristic Symbol Min Max Unit
E10 MDC cycle time t
MDC
400 — ns
E11 MDC pulse width 40 60 % t
MDC
E12 MDC to MDIO output valid — 375 ns
E13 MDC to MDIO output invalid 25 — ns
E14 MDIO input to MDC setup 10 — ns
E15 MDIO input to MDC hold 0 — ns
Valid Data
TXCLK (MII) / EXTAL (RMII)
TXD[n:0]
TXEN,
TXER
E7
E8
E5
E6
CRS, COL
E9