Datasheet

Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 51
DS6 DSPI_SCK to DSPI_SOUT invalid — –5 — ns
DS7 DSPI_SIN to DSPI_SCK input setup — 6 — ns
DS8 DSPI_SCK to DSPI_SIN input hold — 0 — ns
Slave Mode
— DSPI_SCK frequency f
SCK
—f
SYS
 8MHz
DS9 DSPI_SCK cycle time t
SCK
8 f
SYS
—ns
DS10 DSPI_SCK duty cycle — (t
sck
2) – 2.0 (t
sck
2) + 2.0 ns
DS11 DSPI_SCK to DSPI_SOUT valid — — 12 ns
DS12 DSPI_SCK to DSPI_SOUT invalid — 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup — 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold — 7 — ns
DS15 DSPI_SS
active to DSPI_SOUT driven — — 10 ns
DS16 DSPI_SS
inactive to DSPI_SOUT not driven — — 10 ns
1
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin
on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
2
When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].
3
This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],
DCTARn[CPHA], and DCTARn[PBR].
4
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
5
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
Table 36. DSPI module AC timing specifications
1
(continued)
Name Characteristic Symbol Min Max Unit Notes