Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor52
Figure 32. DSPI Classic SPI timing — master Mode
Figure 33. DSPI Classic SPI timing — slave mode
DSPI_PCSn
DSPI_SCK
DSPI_SOUT
DSPI_SIN
DSPI_SCK
(DCTARn[CPOL] = 1)
(DCTARn[CPOL] = 0)
Data
Last Data
First Data
First Data Data Last Data
DS1
DS2
DS2
DS3
DS4
DS6
DS5
DS7
DS8
DSPI_SS
DSPI_SCK
DSPI_SOUT
DSPI_SIN
DSPI_SCK
(DCTARn[CPOL] = 1)
(DCTARn[CPOL] = 0)
Last Data
First Data
Data
Data
First Data
Last Data
DS9
DS10
DS10
DS11
DS12
DS13
DS14
DS15
DS16