Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical characteristics
Freescale Semiconductor54
4.26 1-Wire timing specifications
Specifications for the 1-Wire interface are provided by Maxim Integrated Products, Inc. Please refer to data sheet information
for the appropriate device at www.maxim-ic.com.
4.27 General purpose I/O timing specifications
Figure 35. GPIO timing
4.28 Rapid general purpose I/O timing specifications
RGPIO signals use a mix of pad types: pad_fsr, pad_msr, and pad_ssr. The following timing specifications assume a pad slew
rate setting of 11 and a load of 50 pF.
Table 38. GPIO timing
1
1
These general purpose specifications apply to the following signals: IRQn, all UART signals, all timer
signals, FlexCAN signals, DACKn and DREQn, and all signals configured as GPIO.
Num Characteristic Min Max Unit
G1 FB_CLK high to GPIO output valid — 9 ns
G2 FB_CLK high to GPIO output invalid 1 — ns
G3 GPIO input valid to FB_CLK high 9 — ns
G4 FB_CLK high to GPIO input invalid 1.5 — ns
Table 39. RGPIO timing
Num Characteristic Min Max Unit
RG1 PST_CLK high to RGPIO output valid — 6 ns
RG2 PST_CLK high to RGPIO output Invalid 0.5 — ns
RG3 RGPIO input valid to PST_CLK high 6 — ns
RG4 PST_CLK high to RGPIO input invalid 1.5 — ns
G1
FB_CLK
GPIO Outputs
G2
G3 G4
GPIO Inputs
