Datasheet

Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 55
Figure 36. RGPIO timing
4.29 JTAG and boundary scan timing specifications
All JTAG signals use pad type pad_msr except for TCLK which use pad type pad_fsr. The following timing specifications
assume a pad slew rate setting of 11 and a load of 50 pF.
1
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 40. JTAG and boundary scan timing
Num Characteristics
1
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
Min Max Unit
J1 TCLK frequency of operation DC 25 MHz
J2 TCLK cycle period 40 — ns
J3 TCLK clock pulse width 20 — ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 4 — ns
J6 Boundary scan input data hold time after TCLK rise 20 — ns
J7 TCLK low to boundary scan output data valid — 13 ns
J8 TCLK low to boundary scan output high-Z — 13 ns
J9 TMS, TDI input data setup time to TCLK rise 4 — ns
J10 TMS, TDI input data hold time after TCLK rise 10 — ns
J11 TCLK low to TDO data valid — 12 ns
J12 TCLK low to TDO high-Z — 0 ns
J13 TRST
assert time 32 — ns
J14 TRST
setup time (negation) to TCLK high 8 — ns
RG1
PST_CLK
RGPIO Outputs
RGPIO Inputs
RG2
RG3
RG4