Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Electrical characteristics
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 57
4.30 Debug AC timing specifications
Table 41 lists specifications for the debug AC timing parameters shown in Figure 41 and Table 42.
All debug signals use pad type pad_msr except for PSTCLK which use pad type pad_fsr. The following timing specifications
assume a pad slew rate setting of 11 and a load of 50 pF.
1
Figure 41. Real-time trace AC timing
Figure 42. BDM serial port AC timing
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 41. Debug AC timing specification
Num Characteristic Min Max Units
D0 PSTCLK cycle time 0.5 0.5 1/f
SYS
D1 PSTCLK rising to PSTDDATA valid — 3.0 ns
D2 PSTCLK rising to PSTDDATA invalid 0.5 — ns
D3
DSI-to-DSCLK setup 1 — PSTCLK
D4
1
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative
to the rising edge of PSTCLK.
DSCLK-to-DSO hold 4 — PSTCLK
D5 DSCLK cycle time 5 — PSTCLK
D6 BKPT assertion time 1 — PSTCLK
PSTCLK
PSTDDATA[7:0]
D0
D1
D2
Past
Current
DSCLK
DSI
DSO
Next
Current
D5
D3
D4