Datasheet

Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 59
7 Revision history
Table 43 summarizes revisions to this document.
Table 43. Revision history
Rev. No. Date Summary of changes
2 10 Jun 2009
In Section 2.2, “Supply voltage sequencing” added the following note:
NOTE
All I/O VDD pins must be powered on when the device is functioning,
except when in standby mode.
In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can
be switched off.
Added Section 3.2, “Pinout—169 MAPBGA” and Section 3.3, “Pinout—256 MAPBGA” and updated Tab le 5 with
pin locations.
In Section 4.1, “Absolute maximum ratings”:
• Added USB OTG, USB host, ADC, DAC/ADC, and RTC standby supply voltages
In Section 4.5, “DC electrical specifications”:
• Added RTC standby supply voltage
• Split out Power Supplies and I/O Characteristics to two separate tables
In Section 4.10, “FlexBus timing specifications”:
• Changed maximum frequency to 100MHz and updated specs throughout the table
• Changed FB2 maximum from 5 to 6
• Added notes to Figure 11 and Figure 12
In Section 4.12, “DDR SDRAM controller timing specifications”:
• Changed minimum frequency from 50 to 100
• Changed maximum DD1 from 20 to 10
• Changed DD5 from 2 to 0.5 x t
SDCK
– 1
• Changed DD6 from 1.2 x t
SDCK
to WL + 0.2 x t
SDCK
• Changed DD7 from 1.5 to 0.7
• Changed DD8 from 1.0 to 0.7
• Changed DD9 from 1.0 to 0.5
• Changed DD10 from 0.25 x t
SDCK
+ 0.5 to 0.375 x t
SDCK
In Section 4.17, “SSI timing specifications”:
• Changed S7, S9, S15, and S17 from 10 to 15
In Section 4.22.2, “Transmit signal timing specifications”:
• Changed E5 for MII from 5 to 4
In Section 4.20, “mcPWM timing specifications”:
• Changed G2 from 2 to 1
In Section 4.24, “DSPI timing specifications”:
• Changed DS3 from (2 x 1/fsys) – 2.0 to (t
sck
³ 2) – 2.0
• Changed DS4 from (2 x 1/fsys) – 3.0 to (t
sck
³ 2) – 3.0
• Changed DS7 from 7 to 6
• Changed DS11 from 4 to 12
In Section 4.25, “SBF timing specifications”:
• Changed SB5 maximum from 5 to 3
• Changed SB6 minimum from –5 to 5
In Section 4.26, “1-Wire timing specifications”:
• Added link to 1-wire specs
In Section 4.27, “General purpose I/O timing specifications”:
• Changed G2 from 1.5 to 1
In Section 4.28, “Rapid general purpose I/O timing specifications”:
• Changed RG1 from 3 to 6
• Changed RG2 from 1.5 to 0.5
• Changed RG3 from 3 to 6
In Section 4.29, “JTAG and boundary scan timing specifications”:
• Changed J9-12 and J14 from TBD
In Section 4.30, “Debug AC timing specifications”:
• Changed D2 from 1.5 to 0.5