Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Hardware design considerations
Freescale Semiconductor6
Figure 1. Oscillator/PLL/DAC
power filter
Figure 2 shows an example for isolating the ADC power supply from the I/O supply (EVDD) and ground. Note that in this
power supply the 10 resistor is replaced by a 0 resistor. This will reduce the IR drop into the ADC, limiting additional gain
error.
Figure 2. ADC power filter
Figure 3 shows an example for bypassing the internal core digital power supply for the MPU. This bypass should be applied to
as many IVDD signals as routing allows. Each one should be placed as close to the ball as possible.
Figure 3. IVDD power filter
Figure 4 shows an example for bypassing the external pad ring digital power supply for the MPU. This bypass should be applied
to as many EVDD signals as routing allows. Each one should be placed as close to the ball as possible.
Figure 4. EVDD power filter
VDD_OSC_A_PLL
10
0.1 µF
EVDD Pin
1 µF
GND
VSS_OSC
100 MHz
Board 3.3 V
0
0.1 µF
VDDA_ADC
10 µF
GND
supply
Board 1.2 V
0.1 µF
IVDD
1 µF
GND
supply
Board 3.3 V
0.1 µF
EVDD
1 µF
GND
supply