Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Revision history
Freescale Semiconductor60
3 31 July 2009 Changed 169MAPBGA package to 196MAPBGA throughout.
MCF54410 device now supports a single SSI module and one Ethernet controller with IEEE 1588
support
4 17 Aug 2009 Updated MCF5441x Signal Information and Muxing table with 196MAPBGA pin locations
Changed SD_Dn pin locations on 256 MAPBGA package
Added note to Section 4.6, “Output pad loading and slew rate”
5 29 Jan 2010 Added orderable part numbers
6 Swapped locations of RTC_EXTAL and RTC_XTAL pins in Ta bl e 5 , Figure 7, and Figure 8
Corrected instances of MCF5445x to MCF5441x
Added thermal characteristic s to Ta bl e 7
Added case outline numbers to Tabl e 4 2
Changed PLL supply voltage from “–0.5 to +2.0” to “–0.3 to +4.0” in Tabl e 6
Miscellaneous corrections based on information from shared review comments by team members
7 October 2011 • Updated the pinouts in Tab le 5 , “MCF5441x Signal information and muxing”.
• Updated the Figure 7, “MCF54410 Pinout (196 MAPBGA)”.
• Removed the symbol ADC_IN7/DAC1_OUT from Tabl e 9 , “Latch-up results”.
• Updated Table 11, “I/O electrical specifications”.
• Updated Table 13, “DDR pad drive strengths”.
8 June 2012 • In Tabl e 7 , added the thermal characteristics for the 196 MAPBGA package.
•In Ta bl e 4 2, updated the case outline number for the 196 MAPBGA package from “98ARH98217”
to “98ASA00321D”.
Table 43. Revision history (continued)
Rev. No. Date Summary of changes