Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Hardware design considerations
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 7
Figure 5 shows an example for bypassing the FlexBus power supply for the MPU. This bypass should be applied to as many
FB_VDD signals as routing allows. Each one should be placed as close to the ball as possible.
Figure 5. FB_VDD power filter
2.2 Supply voltage sequencing
Figure 6 shows requirements in the sequencing of the I/O V
DD
(EV
DD
), FlexBus V
DD
(FBV
DD
), SDRAM V
DD
(SDV
DD
), PLL
V
DD
(VDD_OSC_A_PLL), and internal logic/core V
DD
(IV
DD
).
Figure 6. Supply voltage sequencing and separation cautions
The relationships between FBV
DD
, SDV
DD
and EV
DD
are non-critical during power-up and power-down sequences. FBV
DD
(1.8 – 3.3V), SDV
DD
(2.5V or 1.8V) and EV
DD
are specified relative to IV
DD
.
NOTE
All I/O VDD pins must be powered on when the device is functioning, except when in
standby mode.
In standby mode, all I/O VDD pins, except VSTBY_RTC (battery), can be switched off.
Board 1.8–3.3 V
0.1 µF
FB_VDD
1 µF
GND
supply
EV
DD
/FBV
DD
(3.3V)
IV
DD
, VDD_OSC_A_PLL
Time
3.3V
1.5V
0
DC Power Supply Voltage
Notes:
1
Input voltage must not be greater than the supply voltage (EV
DD
, FBV
DD
, SDV
DD
, IV
DD
, or PV
DD
) by more
than 0.5V at any time, including during power-up.
2
Use 25 V/millisecond or slower rise time for all supplies.
2.5V
SDV
DD
(2.5V — DDR)
1.8V
SDV
DD
/FBV
DD
(1.8V — DDR2)
Supplies stable