Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Hardware design considerations
Freescale Semiconductor8
2.2.1 Power-up sequence
If EV
DD
/FBV
DD
/SDV
DD
are powered up with the IV
DD
at 0 V, the sense circuits in the I/O pads cause all pad output drivers
connected to the EV
DD
/FBV
DD
/SDV
DD
to be in a high impedance state. There is no limit on how long after
EV
DD
/FBV
DD
/SDV
DD
powers up before IV
DD
must power up. IV
DD
should not lead the EV
DD
, FBV
DD
, or SDV
DD
by more
than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the
power supplies should be slower than 25 V/millisecond to avoid turning on the internal ESD protection clamp diodes.
2.2.2 Power-down sequence
If IV
DD
/PV
DD
are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IV
DD
and PV
DD
power down before EV
DD
, FBV
DD
, or SDV
DD
must power down. IV
DD
should not lag EV
DD
, FBV
DD
, or SDV
DD
going low by more than 0.4 V during power down or there will be undesired high
current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV
DD
/PV
DD
to 0 V.
2. Drop EV
DD
/FBV
DD
/SDV
DD
supplies.
2.3 Power consumption specifications
Table 3. Estimated power consumption specifications
Characteristic Symbol Typical Unit
Core operating supply current (nominal 1.2 V)
1
Run mode
Wait mode
Doze mode
Stop00 mode
Stop01 mode
Stop02 mode
Stop03 mode
IVDD
127
33
32
9.3
9.2
3.6
3.4
mA
FlexBus operating supply current
Run mode (application dependent)
Wait mode
Doze mode
Stop00 mode
Stop01, Stop02, Stop03 mode
FBVDD
80
49
42
40
28
mA
SDRAM operating supply current (DDR2 at 1.8 V)
Isys(DQ) [8, 2DQS]
Isys(WR) [8, 2DQS]
Isys(RD) [8, 2DQS]
SDRAM input reference current
Isys(REF)
SDRAM termination current
Isys(termRD)
Total SDIDD MPU side
2
SDVDD
SDVREF
SDVTT
3
15
15
1.3
41
75
mA
Oscillator/PLL operating supply current (nominal 3.3 V)
Run, Wait, Doze, Stop00, Stop01 mode
Stop02 mode
Stop03 mode
VDD_OSC_A_PLL
10
6
1
mA