Datasheet
Table Of Contents
- MCF5441x ColdFire Microprocessor Data Sheet
- 1 MCF5441x family comparison
- 2 Hardware design considerations
- 3 Pin assignments and reset states
- 4 Electrical characteristics
- 4.1 Absolute maximum ratings
- 4.2 Thermal characteristics
- 4.3 ESD protection
- 4.4 Static latch-up (LU)
- 4.5 DC electrical specifications
- 4.6 Output pad loading and slew rate
- 4.7 DDR pad drive strengths
- 4.8 Oscillator and PLL electrical characteristics
- 4.9 Reset timing specifications
- 4.10 FlexBus timing specifications
- 4.11 NAND flash controller (NFC) timing specifications
- 4.12 DDR SDRAM controller timing specifications
- 4.13 USB transceiver timing specifications
- 4.14 ULPI timing specifications
- 4.15 eSDHC timing specifications
- 4.16 SIM timing specifications
- 4.17 SSI timing specifications
- 4.18 12-bit ADC specifications
- 4.19 12-bit DAC timing specifications
- 4.20 mcPWM timing specifications
- 4.21 I2C timing specifications
- 4.22 Ethernet assembly timing specifications
- 4.23 32-bit timer module timing specifications
- 4.24 DSPI timing specifications
- 4.25 SBF timing specifications
- 4.26 1-Wire timing specifications
- 4.27 General purpose I/O timing specifications
- 4.28 Rapid general purpose I/O timing specifications
- 4.29 JTAG and boundary scan timing specifications
- 4.30 Debug AC timing specifications
- 5 Package information
- 6 Product documentation
- 7 Revision history
Pin assignments and reset states
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 9
3 Pin assignments and reset states
3.1 Signal multiplexing
The following table lists all the MCF5441x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to the following sections for package diagrams. For a more detailed discussion of the MCF5441x signals,
consult the MCF5441x Reference Manual (MCF54418RM).
NOTE
In this table and throughout this document a single signal within a group is designated
without square brackets (i.e., FB_AD23), while designations for multiple signals within a
group use brackets (i.e., FB_AD[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that
are muxed with GPIO default to their GPIO functionality. See the following table for a list
of the exceptions.
External I/O pad operating supply current (nominal 3.3 V) EVDD
—
3
mA
USB operating supply current (nominal 3.3 V) VDD_USBO,
VDD_USBH 30 mA
ADC operating supply current (nominal 3.3 V)
Speed mode 00
Speed mode 01
VDDA_ADC
14
22
mA
DAC operating supply current (nominal 3.3 V) VDDA_DAC_ADC
11 mA
RTC standby supply current
ISTBY
VSTBY_RTC
17 A
1
Current measured at maximum system clock frequency, all modules active, and default drive
strength with matching load.
2
DDR2 interface power is estimated from the Micron DDR2 data sheet. The numbers given in this
table do not include the actual power consumption of the memory itself. The current drawn by the
memory needs to be added to the values in this table and may be several hundred mA.
3
EVDD values depend on the application, with the restrictions that any single pin cannot exceed
25 mA and that the total power does not exceed the thermal characteristics.
Table 3. Estimated power consumption specifications (continued)
Characteristic Symbol Typical Unit