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M68HC12

Microcontrollers

freescale.com

M68HC12B Family

Data Sheet

M68HC12B

Rev. 9.1

07/2005

Summary of content (334 pages)

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M68HC12B Family Data Sheet M68HC12 Microcontrollers M68HC12B Rev. 9.1 07/2005 freescale.
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M68HC12B Family Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved.
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Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date June, 2001 September, 2001 April, 2002 January, 2003 April, 2003 Revision Level 2.0 3.0 4.0 5.0 6.0 Page Number(s) Description Figure 1-7. BDM Tool Connector — Added NC (no connect) designator to pin 3 29 Figure 18-16.
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List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Chapter 3 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 4 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Chapters M68HC12B Family Data Sheet, Rev. 9.
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Table of Contents Chapter 1 General Description 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Slow-Mode Clock Divider Advisory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Block Diagrams . . . . . . . . . . . . .
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Table of Contents Chapter 2 Register Block 2.1 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Chapter 3 Central Processor Unit (CPU) 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 3.5 3.6 3.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 5 Operating Modes and Resource Mapping 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Normal Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.1 Normal Expanded Wide Mode . . . . . . . .
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Table of Contents Chapter 8 FLASH EEPROM 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.2 FLASH EEPROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3 FLASH EEPROM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.1 FLASH EEPROM Lock Control Register . . . . . .
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Chapter 11 Pulse-Width Modulator (PWM) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 PWM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 PWM Clocks and Concatenate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 PWM Clock Select and Polarity Register . . . . . . . . . . . . . . . .
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Table of Contents 12.5 Using the Output Compare Function to Generate a Square Wave . . . . . . . . . . . . . . . . . . . . . 12.5.1 Sample Calculation to Obtain Period Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3 Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 14 Serial Interface 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 SCI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 15.5.3 BDLC Stop and CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6.0.1 Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6.0.2 Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.8.5 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.5.1 4X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.5.2 Receiving a Message in Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.8.5.3 Transmitting a Message in Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 16.12.4 16.12.5 16.12.6 16.12.7 16.12.8 16.12.9 16.12.10 16.12.11 16.12.12 16.12.13 16.12.14 16.12.15 16.12.16 msCAN12 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . msCAN12 Receiver Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . msCAN12 Receiver Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . msCAN12 Transmitter Flag Register . .
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18.3.6 BDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.7 BDM Shifter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.8 BDM Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.9 BDM CCR Holding Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents M68HC12B Family Data Sheet, Rev. 9.
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Chapter 1 General Description 1.1 Introduction The MC68HC912B32, MC68HC12BE32 and MC68HC(9)12BC32, are 16-bit microcontroller units (MCUs) composed of standard on-chip peripherals. The multiplexed external bus can also operate in an 8-bit narrow mode for interfacing with single 8-bit wide memory in lower-cost systems. There is a slight feature set difference between the four pin-for-pin compatible devices as shown in Table 1-1. Table 1-1.
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General Description 1.
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Slow-Mode Clock Divider Advisory • Serial interfaces: – Asynchronous serial communications interface (SCI) – Synchronous serial peripheral interface (SPI) – J1850 byte data link communication (BDLC), MC68HC912B32 and MC68HC12BE32 only – Controller area network (CAN), MC68HC(9)12BC32 only • Computer operating properly (COP) watchdog timer, clock monitor, and periodic interrupt timer • Slow-mode clock divider • 80-pin quad flat pack (QFP) • Up to 63 general-purpose input/output (I/O) lines • Singl
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General Description 1.
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Block Diagrams 768-BYTE EEPROM ATD CONVERTER CPU12 PERIODIC INTERRUPT SMODN / TAGHI I/O SPI MULTIPLEXED ADDRESS/DATA BUS PWM VDDX × 2 VSSX × 2 DDRA DDRB PORT A PORT B PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 SDI/MISO SDO/MOSI SCK CS/SS PW0 PW1 PW2 PW3 I/O I/O I/O I/O I/O msCAN RxCAN TxCAN I/O I/O I/O I/O I/O I/O PS
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General Description 1.5 Ordering Information The M68HC12B-series devices are available in 80-pin quad flat pack (QFP) packaging and are shipped in 2-piece sample packs, 84-piece trays, or 420-piece bricks. Operating temperature range, package type, and voltage requirements are specified when ordering the specific device. Documents to assist in product selection are available from the Freescale Literature Distribution Center or your local Freescale sales offices.
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Pinout and Signal Descriptions PORT S PORT T PDLC0 / DLCRx PDLC1 / DLCTx PDLC2 PDLC3 PDLC4 PDLC5 PDLC6 VFP/NC(1) PS7 / CS/SS PS6 / SCK PS5 / SDO/MOSI PS4 / SDI/MISO PS3 PS2 PS1 / TxD PS0 / RxD 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP6 PP7 80 79 PORT P Shaded pins are power and ground PP5 1 60 VSSA PP4 2 59 VDDA PW3 / PP3 3 58 PAD7 / AN7 PW2 / PP2 4 57 PAD6 / AN6 PW1/ PP1 5 56 PAD5 / AN5 PW0/ PP0 6 55 PAD4 / AN4 IOC0 / PT0 7 54
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General Description PORT S PORT T RxCAN TxCAN PCAN2 PCAN3 PCAN4 PCAN5 PCAN6 VFP/NC(1) PS7 / CS/SS PS6 / SCK PS5 / SDO/MOSI PS4 / SDI/MISO PS3 PS2 PS1 / TxD PS0 / RxD 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP6 PP7 80 79 PORT P Shaded pins are power and ground PP5 1 60 VSSA PP4 2 59 VDDA PW3 / PP3 3 58 PAD7 / AN7 PW2 / PP2 4 57 PAD6 / AN6 PW1/ PP1 5 56 PAD5 / AN5 PW0/ PP0 6 55 PAD4 / AN4 IOC0 / PT0 7 54 PAD3 / AN3 IOC1 / PT1 8
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Pinout and Signal Descriptions 1.6.2.5 VFP (MC68HC912B32 and MC68HC912BC32 only) VFP is the FLASH EEPROM programming voltage and supply voltage during normal operation for the MC68HC912B32 and MC68HC912BC32 only. Table 1-2.
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General Description C EXTAL 10 MΩ MCU 2xE CRYSTAL C XTAL Figure 1-5. Common Crystal Connections 2xE CMOS-COMPATIBLE EXTERNAL OSCILLATOR EXTAL MCU XTAL NC Figure 1-6. External Oscillator Connections 1.6.3.2 ECLK ECLK is the output connection for the internal bus clock and is used to demultiplex the address and data and is used as a timing reference. ECLK frequency is equal to one half the crystal frequency out of reset.
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Pinout and Signal Descriptions selectable (interrupt control register, INTCR). IRQ is always configured to level-sensitive triggering at reset. When the MCU is reset, the IRQ function is masked in the condition code register. This pin is always an input and can always be read. In special modes, it can be used to apply external EEPROM VPP in support of EEPROM testing. External VPP is not needed for normal EEPROM program and erase cycles.
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General Description 1.6.3.8 ADDR15–ADDR0 and DATA15–DATA0 ADDR15–ADDR0 and DATA15–DATA0 are the external address and data bus pins. They share functions with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses. In expanded wide mode, ports A and B multiplex 16-bit data and address buses. The PA7–PA0 pins multiplex ADDR15–ADDR8 and DATA15–DATA8. The PB7–PB0 pins multiplex ADDR7–ADDR0 and DATA7–DATA0.
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Pinout and Signal Descriptions Table 1-3. Signal Description Summary Pin Name Pin Number PW3–PW0 3–6 ADDR7–ADDR0 DATA7–DATA0 25–18 ADDR15–ADDR8 DATA15–DATA8 46–39 IOC7–IOC0 16–12, 9–7 PAI 16 AN7–AN0 58–51 Description Pulse-width modulator channel outputs External bus pins share function with general-purpose I/O ports A and B. In single-chip modes, the pins can be used for I/O. In expanded modes, the pins are used for the external buses.
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General Description 1.6.4 Port Signals The MCU incorporates eight ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O. In addition to the pins described here, each port consists of: • A data register which can be read and written at any time • With the exception of port AD and PE1–PE0, a data direction register which controls the direction of each pin After reset, all port pins are configured as input.
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Pinout and Signal Descriptions the corresponding bit in port A an output; clearing a bit in DDRA makes the corresponding bit in port A an input. The default reset state of DDRA is all 0s. When the PUPA bit in the PUCR register is set, all port A input pins are pulled up internally by an active pullup device. This bit has no effect if the port is being used in expanded modes as the pullups are inactive.
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General Description 1.6.4.4 Port DLC The MC68HC912B32 and MC68HC12BE32 contain the port DLC. Byte data link communications (BDLC) pins can be configured as general-purpose I/O port DLC. When BDLC functions are not enabled, the port has seven general-purpose I/O pins, PDLC6–PDLC0. The port DLC control register (DLCSCR) controls port DLC function. The BDLC function, enabled with the BDLCEN bit, takes precedence over other port functions.
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Pinout and Signal Descriptions 1.6.4.7 Port P The four pulse-width modulation channel outputs share general-purpose port P pins. The PWM function is enabled with the PWM enable register (PWEN). Enabling PWM pins takes precedence over the general-purpose port. When pulse-width modulation is not in use, the port pins may be used for general-purpose I/O. The port P data direction register (DDRP) determines pin direction of port P when used for general-purpose I/O.
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General Description 1.6.5 Port Pullup, Pulldown, and Reduced Drive MCU ports can be configured for internal pullup. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced drive causes a slight increase in transition time depending on loading and should be used only for ports which have a light loading. Table 1-5 summarizes the port pullup default status and controls. Table 1-5.
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RSET IN VDD0 VDD1 VDDX0 VDDX1 VDDAD 1 RESET Freescale Semiconductor 2 U2 MC34064 DN 3 GROUND Y1 49 50 VFP 69 33 34 32 17 38 37 36 35 29 MODA 28 MODB 27 26 R14 M68HC12B Family Data Sheet, Rev. 9.1 C2 C1 R32 4.7 K RESET JP1 GND VFP VDD 1 2 3 4 5 6 1 2 3 4 5 6 HEADER 6 VDD VDD 4 3 VDD R3 4.
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IN RSET 1 DN 3 GROUND Y1 R1 M68HC12B Family Data Sheet, Rev. 9.1 C2 C1 R32 4.
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Chapter 2 Register Block 2.1 Introduction The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG15–REG11 in the register initialization register (INITRG). INITRG establishes the upper five bits of the register block’s 16-bit address. The register block occupies the first 512 bytes of the 2-Kbyte block. Default addressing (after reset) is indicated in Figure 2-1.
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Register Block 2.2 Registers Addr. $0000 Register Name Port A Data Register Read: (PORTA) Write: See page 86. Reset: $0001 Port B Data Register Read: (PORTB) Write: See page 87. Reset: $0002 Data Direction Register A Read: (DDRA) Write: See page 86. Reset: $0003 $0004 Data Direction Register B Read: (DDRB) Write: See page 87.
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Registers Addr. Register Name $0010 RAM Initialization Register Read: (INITRM) Write: See page 80. Reset: $0011 Register Initialization Register Read: (INITRG) Write: See page 80. Reset: $0012 EEPROM Initialization Register Read: (INITEE) Write: See page 81. Reset: $0013 Miscellaneous Mapping Control Read: Register (MISC) Write: See page 82. Reset: $0014 Real-Time Interrupt Control Read: Register (RTICTL) Write: See page 118.
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Register Block Addr.
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Registers Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 PWM Scale Register 1 (PWSCAL1) Write: See page 132. Reset: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 PWM Scale Counter Register 1 Read: (PWSCNT1) Write: See page 132. Reset: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $0047 0 0 0 0 0 0 0 0 $0048 PWM Channel Counter Register 0 Read: (PWCNT0) Write: See page 133.
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Register Block Addr. $0052 Register Name PWM Channel Duty Register 2 Read: (PWDTY2) Write: See page 135. Reset: $0053 PWM Channel Duty Register 3 Read: (PWDTY3) Write: See page 135. Reset: $0054 PWM Control Register Read: (PWCTL) Write: See page 136. Reset: $0055 PWM Special Mode Register Read: (PWTST) Write: See page 137. Reset: $0056 Port P Data Register Read: (PORTP) Write: See page 137. Reset: $0057 $0058 Port P Data Direction Register Read: (DDRP) Write: See page 138.
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Registers Addr. $0065 Register Name Bit 7 ATD Control Register 5 Read: (ATDCTL5) Write: See page 282. Reset: 6 5 4 3 2 1 Bit 0 S8CM SCAN MULT CD CC CB CA 0 0 0 0 0 0 0 0 0 0 0 0 CC2 CC1 CC0 ATD Status Register Read: (ATDSTAT) Write: See page 284. Reset: SCF $0066 0 0 0 0 0 0 0 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 $0067 ATD Status Register Read: (ATDSTAT) Write: See page 284.
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Register Block Addr. Bit 7 6 5 4 3 2 1 Bit 0 ATD Result Register 2 Read: (ADRx2L) Write: See page 286. Reset: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATD Result Register 3 Read: (ADRx3H) Write: See page 286. Reset: Bit 15 Bit 14 Bit 13 Bit 12 Bit 10 Bit 9 Bit 8 $0076 Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 $0077 ATD Result Register 3 Read: (ADRx3L) Write: See page 286. Reset: ATD Result Register 4 Read: (ADRx4H) Write: See page 286.
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Registers Addr. $0081 Register Name Timer Compare Force Register Read: (CFORC) Write: See page 141. Reset: $0082 Timer Output Compare 7 Mask Read: Register (OC7M) Write: See page 143. Reset: $0083 Timer Output Compare 7 Data Read: Register (OC7D) Write: See page 143.
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Register Block Addr. $008E Register Name Timer Interrupt Flag Register 1 Read: (TFLG1) Write: See page 148. Reset: $008F Timer Interrupt Flag Register 2 Read: (TFLG2) Write: See page 148. Reset: $0090 Timer Input Capture/Output Read: Compare 0 Register High (TC0H) Write: See page 149. Reset: $0091 Timer Input Capture/Output Read: Compare 0 Register Low (TC0L) Write: See page 149. Reset: $0092 Timer Input Capture/Output Read: Compare 1 Register High (TC1H) Write: See page 149.
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Registers Addr. $009A Register Name Timer Input Capture/Output Read: Compare 5 Register High (TC5H) Write: See page 150. Reset: $009B Timer Input Capture/Output Read: Compare 5 Register Low (TC5L) Write: See page 150. Reset: $009C Timer Input Capture/Output Read: Compare 6 Register High (TC6H) Write: See page 151. Reset: $009D Timer Input Capture/Output Read: Compare 6 Register Low (TC6L) Write: See page 151.
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Register Block Addr. $00A6 Register Name 16-Bit Modulus Down-Counter Read: Control Register (MCCTL) Write: See page 179. Reset: $00A7 16-Bit Modulus Down-Counter Flag Read: Register (MCFLG) Write: See page 180. Reset: $00A8 Input Control Pulse Accumulators Read: Control Register (ICPACR) Write: See page 181. Reset: $00A9 $00AA $00AB $00AC $00AD Delay Counter Control Register Read: (DLYCT) Write: See page 181. Reset: Input Control System Control Read: Register (ICSYS) Write: See page 182.
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Registers Addr. $00B3 Register Name 8-Bit Pulse Accumulator Holding Read: Register 2 (PA2H) Write: See page 186. Reset: $00B4 8-Bit Pulse Accumulator Holding Read: Register 1 (PA1H) Write: See page 186. Reset: $00B5 8-Bit Pulse Accumulator Holding Read: Register 0 (PA0H) Write: See page 186. Reset: $00B6 Modulus Down-Counter Count Read: Register (MCCNT) Write: See page 187. Reset: $00B7 Modulus Down-Counter Count Read: Register (MCCNT) Write: See page 187.
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Register Block Addr. $00BF $00C0 $00C1 Register Name Timer Input Capture Holding Read: Register 3 (TC3H) Write: See page 188. Reset: SCI 0 Baud Rate Control Register Read: High (SC0BDH) Write: See page 194. Reset: SCI 0 Baud Rate Control Register Read: Low (SC0BDL) Write: See page 194. Reset: $00C2 SCI Control Register 1 Read: (SC0CR1) Write: See page 195. Reset: $00C3 SCI Control Register 2 Read: (SC0CR2) Write: See page 197.
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Registers Addr. $00D2 Register Name SPI Baud Rate Register Read: (SP0BR) Write: See page 206. Reset: Bit 7 6 5 4 3 0 0 0 0 0 2 1 Bit 0 SPR2 SPR1 SPR0 0 0 0 0 0 0 0 0 WCOL 0 MODF 0 0 0 0 SPI Status Register Read: (SP0SR) Write: See page 207. Reset: SPIF $00D3 0 0 0 0 0 0 0 0 $00D4 Reserved R R R R R R R R $00D5 SPI Data Register Read: (SP0DR) Write: See page 207.
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Register Block Addr. $00F1 Register Name EEPROM Block Protect Register Read: (EEPROT) Write: See page 95. Reset: $00F2 Read: EEPROM Test Register (EETST) Write: See page 95. Reset: $00F3 EEPROM Control Register Read: (EEPROG) Write: See page 96. Reset: $00F4 FLASH EEPROM Lock Control Read: Register (FEELCK)(1) Write: See page 100. Reset: $00F5 FLASH EEPROM Configuration Read: Register (FEEMCR)(1) Write: See page 100. Reset: $00F6 FLASH EEPROM Test Read: Register (FEETST)(1) Write: See page 100.
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Registers Addr. $00FD Register Name Port DLC Control Register Read: (DLCSCR)(2) Write: See page 241. Reset: Bit 7 6 5 4 3 0 0 0 0 0 2 1 Bit 0 BDLCEN PUPDLC RDPDLC 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 U U U U U U U DDDLC6 DDDLC5 DDDLC4 DDDLC3 DDDLC2 DDDLC1 DDDLC0 0 0 0 0 0 0 SLPRQ SFTRES 0 0 1 LOOPB WUPM CLKSRC Port DLC Data Register Read: (PORTDLC)(2) Write: See page 242.
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Register Block Addr. $010D $010E $010F $0110 Register Name Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R msCAN12 Receive Error Counter Read: RXERR7 (CRXERR)(3) Write: See page 271. Reset: 0 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0 0 0 0 0 0 0 msCAN12 Transmit Error Counter Read: TXERR7 (CTXERR)(3) Write: See page 272.
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Registers Addr. $011A Register Name msCAN12 Identifier Acceptance Read: Register 6 (CIDAR6)(3) Write: See page 273. Reset: $011B msCAN12 Identifier Acceptance Read: Register 7 (CIDAR7)(3) Write: See page 273. Reset: $011C msCAN12 Identifier Mask Read: Register 4 (CIDMR4)(3) Write: See page 274. Reset: $011D msCAN12 Identifier Mask Read: Register 5 (CIDMR5)(3) Write: See page 274. Reset: $011E msCAN12 Identifier Mask Read: Register 6 (CIDMR6)(3) Write: See page 274.
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Register Block Addr. Register Name Bit 7 6 5 4 3 2 1 $0160 ↓ $016F TRANSMIT BUFFER 1 (TX1)(3) — SEE 16.3.3 Transmit Structures $0170 ↓ $017F TRANSMIT BUFFER 2 (Tx2)(3) — SEE 16.3.3 Transmit Structures = Unimplemented R = Reserved Bit 0 U = Unaffected Notes: 1. Available only on MC68HC912B32 and MC68HC912BC32 devices. 2. Available only on MC68HC912B32 and MC68HC12BE32 devices. 3. Available only on MC68HC(9)12BC32 devices. Figure 2-1.
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Chapter 3 Central Processor Unit (CPU) 3.1 Introduction The CPU12 is a high-speed, 16-bit processor unit. It has full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set. The CPU12 allows instructions with odd byte counts, including many single-byte instructions. This provides efficient use of ROM space.
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Central Processor Unit (CPU) 3.3 CPU Registers This section describes the CPU registers. 3.3.1 Accumulators A and B Accumulators A and B are general-purpose 8-bit accumulators that contain operands and results of arithmetic calculations or data manipulations. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 A7 A6 A5 A4 A3 A2 A1 A0 Reset: Unaffected by reset Figure 3-2.
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CPU Registers 3.3.3 Index Registers X and Y Index registers X and Y are used for indexed addressing. Indexed addressing adds the value in an index register to a constant or to the value in an accumulator to form the effective address of the operand. Index registers X and Y can also serve as temporary data storage locations. NOTE The LDX and STX instructions can be used to manipulate data in and out of index register X. Figure 3-5.
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Central Processor Unit (CPU) 3.3.5 Program Counter The program counter contains the address of the next instruction to be executed. The program counter can also serve as an index register in all indexed addressing modes except autoincrement and autodecrement. Figure 3-8. Program Counter (PC) Read: Write: Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Reset: Unaffected by reset 3.3.
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Data Types 3.4 Data Types The CPU12 supports four data types: 1. Bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. There are no special requirements for alignment of instructions or operands. 3.
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Central Processor Unit (CPU) Table 3-1. Addressing Mode Summary (Continued) Addressing Mode Source Format Abbreviation Description Indexed-Indirect 16-bit offset INST [oprx16,xysp] [IDX2] Pointer to operand is found at 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) Indexed-Indirect D accumulator offset INST [D,xysp] [D,IDX] Pointer to operand is found at x, y, sp, or pc plus the value in D 3.
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Opcodes and Operands 3.7 Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the opcode map.
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Central Processor Unit (CPU) M68HC12B Family Data Sheet, Rev. 9.
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Chapter 4 Resets and Interrupts 4.1 Introduction Resets and interrupts are exceptions. Each exception has a 16-bit vector that points to the memory location of the associated exception-handling routine. Vectors are stored in the upper 128 bytes of the standard 64-Kbyte address map. The six highest vector addresses are used for resets and non-maskable interrupt sources.
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Resets and Interrupts Table 4-1.
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Maskable Interrupts Table 4-2.
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Resets and Interrupts 4.4 Latching of Interrupts XIRQ is always level triggered and IRQ can be selected as a level-triggered interrupt. These level-triggered interrupt pins should be released only during the appropriate interrupt service routine. Generally, the interrupt service routine will handshake with the interrupting logic to release the pin. In this way, the MCU will never start the interrupt service sequence only to determine that there is no longer an interrupt source.
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Resets 4.5.2 Highest Priority I Interrupt Register Address: $001F Bit 7 6 1 1 1 1 Read: Write: Reset: 5 4 3 2 1 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 1 1 0 0 1 Bit 0 0 0 Figure 4-2. Highest Priority I Interrupt Register (HPRIO) Read: Anytime Write: Only if I bit in CCR = 1 (interrupts inhibited) To give a maskable interrupt source highest priority, write the low byte of the vector address to the HPRIO register.
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Resets and Interrupts 4.6.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 4.7 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known startup states, as described here. 4.7.1 Operating Mode and Memory Map The states of the BKGD, MODA, and MODB pins during reset determine the operating mode and default memory mapping.
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Interrupt Recognition 4.7.7 Other Resources The timer, serial communications interface (SCI), serial peripheral interface (SPI), byte data link controller (BDLC), pulse-width modulator (PWM), analog-to-digital converter (ATD), and MSCAN are off after reset. 4.8 Interrupt Recognition Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared. When an interrupt request is recognized, the CPU responds at the completion of the instruction being executed.
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Resets and Interrupts M68HC12B Family Data Sheet, Rev. 9.
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Chapter 5 Operating Modes and Resource Mapping 5.1 Introduction The MCU can operate in eight different modes. Each mode has a different default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. 5.2 Operating Modes The states of the BKGD, MODB, and MODA pins during reset determine the operating mode after reset.
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Operating Modes and Resource Mapping 5.2.1 Normal Operating Modes These modes provide three operating configurations. Background debugging is available in all three modes, but must first be enabled for some operations by means of a BDM command. BDM can then be made active by another BDM command. 5.2.1.1 Normal Expanded Wide Mode The 16-bit external address and data buses use ports A and B. ADDR15–ADDR8 and DATA15–DATA8 are multiplexed on port A. ADDR7–ADDR0 and DATA7–DATA0 are multiplexed on port B. 5.2.1.
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Internal Resource Mapping 5.2.2.4 Special Peripheral Mode The CPU is not active in this mode. An external master can control on-chip peripherals for testing purposes. It is not possible to change to or from this mode without going through reset. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both modes. 5.2.
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Operating Modes and Resource Mapping Table 5-2. Mapping Precedence Precedence Resource 1 BDM ROM (if active) 2 Register space 3 RAM 4 EEPROM 5 FLASH EEPROM/ROM 6 External memory 5.4 Mode and Resource Mapping Registers This section describes the mode and resource mapping registers. 5.4.1 Mode Register The mode register (MODE) controls the MCU operating mode and various configuration options. This register is not in the map in peripheral mode.
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Mode and Resource Mapping Registers ESTR — E Clock Stretch Enable Bit ESTR determines if the E clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. ESTR is always 1 in expanded modes since it is required for address demultiplexing and must follow stretched cycles.
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Operating Modes and Resource Mapping 5.4.2 Register Initialization Register After reset, the 512-byte register block resides at location $0000 but can be reassigned to any 2-Kbyte boundary within the standard 64-Kbyte address space. Mapping of internal registers is controlled by five bits in the register initialization register (INITRG). The register block occupies the first 512 bytes of the 2-Kbyte block.
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Mode and Resource Mapping Registers 5.4.4 EEPROM Initialization Register The MCU has 768 bytes of EEPROM which are activated by the EEON bit in the EEPROM initialization register (INITEE). Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset, EEPROM address space begins at location $0D00 but can be mapped to any 4-Kbyte boundary within the standard 64-Kbyte address space.
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Operating Modes and Resource Mapping Address: $0013 Bit 7 6 5 4 3 2 1 Bit 0 0 NDRF RFSTR1 RFSTR0 EXSTR1 EXSTR0 MAPROM ROMON Expanded modes: 0 0 0 0 1 1 0 0 Single-chip modes: 0 0 0 0 1 1 1 1 Read: Write: Reset states: Figure 5-5. Miscellaneous Mapping Control Register (MISC) Read: Anytime Write: Once in normal modes; anytime in special modes NDRF — Narrow Data Bus for Register-Following Map Bit This bit enables a narrow bus feature for the 512-byte register-following map.
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Memory Map MAPROM — FLASH EEPROM/ROM Map Bit This bit determines the location of the on-chip FLASH EEPROM/ROM. In expanded modes, it is reset to 0. In single-chip modes, it is reset to 1. If ROMON is 0, this bit has no meaning or effect. 1 = FLASH EEPROM/ROM is located from $8000 to $FFFF. 0 = FLASH EEPROM/ROM is located from $0000 to $7FFF. ROMON — FLASH EEPROM/ROM Enable Bit In expanded modes, ROMON is reset to 0. In single-chip modes, it is reset to 1.
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Operating Modes and Resource Mapping M68HC12B Family Data Sheet, Rev. 9.
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Chapter 6 Bus Control and Input/Output (I/O) 6.1 Introduction Internally, the MCU has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or 16 bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8-bit or 16-bit data. 6.2 Detecting Access Type from External Signals The external signals LSTRB, R/W, and A0 can be used to determine the type of bus access that is taking place.
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Bus Control and Input/Output (I/O) be set. In this special case of expanded mode and EME set, the port E data register (PORTE) and port E data direction register (DDRE) are removed from the on-chip memory map and become external accesses so port E may be rebuilt externally. 6.3.
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Registers 6.3.3 Port B Data Register Address: $0001 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Reset: Unaffected by reset Alternate functions: Expanded wide and peripheral: ADDR7 DATA7 ADDR6 DATA6 ADDR5 DATA5 ADDR4 DATA4 ADDR3 DATA3 ADDR2 DATA2 ADDR1 DATA1 ADDR0 DATA0 Expanded narrow: ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Figure 6-3.
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Bus Control and Input/Output (I/O) 6.3.5 Port E Data Register Address: $0008 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 0 0 0 0 0 0 0 0 DBE MODB or IPIPE1 MODA or IPIPE0 ECLK LSTRB or TAGLO R/W IRQ XIRQ Reset: Alternate function: Figure 6-5.
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Registers PE1 and PE0 are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can be read regardless of whether the alternate interrupt functions are enabled. This register is not in the map in peripheral mode and expanded modes while the EME control bit is set. 6.3.
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Bus Control and Input/Output (I/O) CGMTE — CGM Test Output Enable Normal: Write once Special: Write anytime except the first time. This bit is read at anytime. 1 = PE6 is a test signal output from the CGM module (no effect in single chip or normal expanded modes). PIPOE = 1 overrides this function and forces PE6 to be a pipe status output signal. 0 = PE6 is a general-purpose I/O or pipe output. PIPOE — Pipe Signal Output Enable Bit Normal: Write once Special: Write anytime except the first time.
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Registers 6.3.8 Pullup Control Register Address: $000C Read: Bit 7 6 5 0 0 0 0 0 0 Write: Reset: 4 PUPE 1 3 2 0 0 0 0 1 Bit 0 PUPB PUPA 0 0 = Unimplemented Figure 6-8. Pullup Control Register (PUCR) Read: Anytime, if register is in the map Write: Anytime, if register is in the map These bits select pullup resistors for any pin in the corresponding port that is currently configured as an input. This register is not in the map in peripheral mode.
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Bus Control and Input/Output (I/O) 6.3.9 Reduced Drive of I/O Lines Address: $000D Read: Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 RDPE 0 2 0 1 Bit 0 RDPB RDPA 0 0 0 = Unimplemented Figure 6-9. Reduced Drive of I/O Lines (RDRIV) Read: Anytime, if register is in the map Write: Once in normal modes; anytime, except the first time, in special modes These bits select reduced drive for the associated port pins.
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Chapter 7 EEPROM 7.1 Introduction The MCU is electrically erasable, programmable read-only memory (EEPROM) serves as a 768-byte non-volatile memory which can be used for frequently accessed static data or as fast access program code. The MCU’s EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words, or misaligned words. Access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations.
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EEPROM At bus frequencies below 1 MHz, the RC clock must be turned on for program/erase. $_D00 BPROT4 256 BYTES $_E00 BPROT3 256 BYTES $_F00 BPROT2 128 BYTES $_F80 $_FC0 BPROT1 BPROT0 Figure 7-1. EEPROM Block Protect Mapping 7.3 EEPROM Control Registers This section describes the EEPROM control registers. 7.3.1 EEPROM Module Configuration Register Address: $00F0 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 EESWAI PROTLCK EERC 1 1 1 1 1 1 0 0 Figure 7-2.
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EEPROM Control Registers 7.3.2 EEPROM Block Protect Register Address: $00F1 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 BRPROT4 BRPROT3 BRPROT2 BRPROT1 BRPROT0 1 1 1 1 1 1 1 1 Figure 7-3. EEPROM Block Protect Register (EEPROT) The EEPROM block protect register (EEPROT) prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. BPROT4–BPROT0 — EEPROM Block Protection Bit 0 = Associated EEPROM block can be programmed and erased.
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EEPROM MARG — Program and Erase Voltage Margin Test Enable Bit 0 = Normal operation 1 = Program and erase margin test This bit is used to evaluate the program/erase voltage margin. EECPD — Charge Pump Disable Bit 0 = Charge pump is turned on during program/erase. 1 = Disable charge pump. EECPRD — Charge Pump Ramp Disable Bit 0 = Charge pump is turned on progressively during program/erase. 1 = Disable charge pump controlled ramp up. Known to enhance write/erase endurance of EEPROM cells.
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EEPROM Control Registers If BYTE = 1 and test mode is not enabled, only the location specified by the address written to the programming latches will be erased. The operation will be a byte or an aligned word erase depending on the size of written data. ERASE — Erase Control Bit 0 = EEPROM configuration for programming or reading 1 = EEPROM configuration for erasure Read anytime. Write anytime if EEPGM = 0. Configures the EEPROM for erasure or programming.
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EEPROM M68HC12B Family Data Sheet, Rev. 9.
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Chapter 8 FLASH EEPROM 8.1 Introduction The 32-Kbyte FLASH EEPROM module for the MC68HC912B32 and MC68HC912BC32 serves as electrically erasable and programmable, non-volatile ROM emulation memory. The module can be used for program code that must either execute at high speed or is frequently executed, such as operating system kernels and standard subroutines, or it can be used for static data which is read frequently.
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FLASH EEPROM 8.3.1 FLASH EEPROM Lock Control Register Address: $00F4 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 LOCK 0 0 0 0 0 0 0 0 Figure 8-1. FLASH EEPROM Lock Control Register (FEELCK) In normal modes, the LOCK bit can be written only once after reset. LOCK — Lock Register Bit 0 = Enable write to FEEMCR register. 1 = Disable write to FEEMCR register. 8.3.
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FLASH EEPROM Registers GADR — Gate/Drain Stress Test Select Bit 0 = Selects the drain stress circuitry 1 = Selects the gate stress circuitry HVT — Stress Test High Voltage Status Bit 0 = High voltage not present during stress test 1 = High voltage present during stress test FENLV — Enable Low Voltage Bit 0 = Disables low voltage transistor in current reference circuit 1 = Enables low voltage transistor in current reference circuit FDISVFP — Disable Status VFP Voltage Lock Bit When the VFP pin is below norm
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FLASH EEPROM 8.3.4 FLASH EEPROM Control Register Address: $00F7 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 FEESWAI SVFP ERAS LAT ENPE 0 0 0 0 0 0 0 0 Figure 8-4. FLASH EEPROM Control Register (FEECTL) This register controls the programming and erasure of the FLASH EEPROM. FEESWAI — FLASH EEPROM Stop in Wait Control Bit 0 = Do not halt FLASH EEPROM clock when in wait mode. 1 = Halt FLASH EEPROM clock when in wait mode.
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Operation FLASH EEPROM module control registers may be read or written while ENPE is asserted. If ENPE is asserted and LAT is negated on the same write access, no programming or erasure will be performed. Table 8-1. Effects of ENPE, LAT, and ERAS on Array Reads ENPE LAT ERAS Result of Read 0 0 — Normal read of location addressed 0 1 0 Read of location being programmed 0 1 1 Normal read of location addressed 1 — — Read cycle is ignored 8.
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FLASH EEPROM 8.4.3.2 Program/Erase Verification When programming or erasing the FLASH EEPROM array, a special verification method is required to ensure that the program/erase process is reliable and also to provide the longest possible life expectancy. This method requires stopping the program/erase sequence at periods of tPPULSE (tEPULSE for erasing) to determine if the FLASH EEPROM is programmed/erased.
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Programming the FLASH EEPROM 8.5 Programming the FLASH EEPROM Programming the FLASH EEPROM is accomplished by this step-by-step procedure. The VFP pin voltage must be at the proper level prior to executing step 4 the first time. 1. Apply program/erase voltage to the VFP pin. 2. Clear ERAS and set the LAT bit in the FEECTL register to establish program mode and enable programming address and data latches. 3. Write data to a valid address. The address and data are latched.
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FLASH EEPROM START PROG TURN ON VFP CLEAR MARGIN FLAG CLEAR PROGRAM PULSE COUNTER (nPP) CLEAR ERAS SET LAT WRITE DATA TO ADDRESS SET ENPE DELAY FOR DURATION OF PROGRAM PULSE (tPPULSE) CLEAR ENPE SET MARGIN FLAG DELAY BEFORE VERIFY (tVPROG) IS MARGIN FLAG SET? NO YES DECREMENT nPP COUNTER INCREMENT nPP COUNTER READ LOCATION DATA CORRECT? YES NO NO nPP = 0? nPP = 50? YES DATA CORRECT? NO YES NO YES CLEAR LAT GET NEXT ADDRESS/DATA NO LOCATION FAILED TO PROGRAM DONE? YES TURN OFF VFP DONE PROG
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Erasing the FLASH EEPROM 8.6 Erasing the FLASH EEPROM This sequence demonstrates the recommended procedure for erasing the FLASH EEPROM. The VFP pin voltage must be at the proper level prior to executing step 4 the first time. 1. Turn on VFP. Apply program/erase voltage to the VFP pin. 2. Set the LAT bit and ERAS bit to configure the FLASH EEPROM for erasing. 3. Write to any valid address in the FLASH array.
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FLASH EEPROM START ERASE TURN ON VFP CLEAR MARGIN FLAG CLEAR ERASE PULSE COUNTER (nEP) SET ERAS SET LAT WRITE TO ARRAY SET ENPE DELAY FOR DURATION OF ERASE PULSE (tEPULSE) CLEAR ENPE SET MARGIN FLAG DELAY BEFORE VERIFY (tVERASE) IS MARGIN FLAG SET? NO INCREMENT nEP COUNTER READ ARRAY YES DECREMENT nEP COUNTER ARRAY ERASED? YES NO NO nEP = 0? nEP = 5? YES ARRAY ERASED? NO YES NO YES CLEAR LAT TURN OFF VFP ARRAY ERASED ARRAY FAILED TO ERASE Figure 8-6.
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Program/Erase Protection Interlocks 8.7 Program/Erase Protection Interlocks The FLASH EEPROM program and erase mechanisms provide maximum protection from accidental programming or erasure. The voltage required to program/erase the FLASH EEPROM (VFP) is supplied via an external pin. If VFP is not present, no programming/erasing will occur. Furthermore, the program/erase voltage will not be applied to the FLASH EEPROM unless turned on by setting a control bit (ENPE).
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FLASH EEPROM M68HC12B Family Data Sheet, Rev. 9.
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Chapter 9 Read-Only Memory (ROM) 9.1 Introduction The MC68HC12BE32 and MC68HC12BC32 contain 32 Kbytes of read-only memory (ROM). The ROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. Access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. 9.2 ROM Array After reset, the ROM array is located from addresses $8000 to $FFFF in single-chip mode.
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Read-Only Memory (ROM) M68HC12B Family Data Sheet, Rev. 9.
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Chapter 10 Clock Generation Module (CGM) 10.1 Introduction The clock generation module (CGM) generates the system clocks and generates and controls the timing of the reset and power-on reset (POR) logic. The CGM is composed of: • Clock selection and generation circuitry • Slow-mode clock divider • Reset and stop generation timing and control NOTE Older device mask sets do not support the slow-mode clock divider feature. Register $00E0 is reserved in older devices and provides no function.
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Clock Generation Module (CGM) 10.3 Register Map Addr. $0014 $0015 Register Name Real-Time Interrupt Control Read: Register (RTICTL) Write: See page 118. Reset: Real-Time Interrupt Flag Register Read: (RTIFLG) Write: See page 119. Reset: $0016 Read: COP Control Register (COPCTL) Write: See page 119. Reset: $0017 Arm/Reset COP Timer Read: Register (COPRST) Write: See page 120. Reset: $00E0 Slow Mode Divider Register Read: (SLOW) Write: See page 117.
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Clock Selection and Generation OSCILLATOR T1 CLOCK T2 CLOCK T3 CLOCK T4 CLOCK E CLOCK P CLOCK Figure 10-3. Internal Clock Relationships in Normal Run Modes OSCILLATOR T1 CLOCK T2 CLOCK T3 CLOCK T4 CLOCK E CLOCK (G)(1) P CLOCK (G)(1) E CLOCK (GBT)(2) P CLOCK (GBT)(2) Notes: 1. Driven by slow clock divider in wait mode. Drives on-chip peripherals except BDLC and timer. 2. Remains at oscillator divided by 2 rate in wait mode. Drives BDLC and timer. Figure 10-4.
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Clock Generation Module (CGM) 10.5 Slow Mode Divider The slow mode divider is included to deliver a variable bus frequency to the MCU in wait mode. The bus clocks are derived from the constant P clock. The slow clock counter divides the P clock and E clock frequency in powers of 2, up to 128. When the slow control register is cleared or the part is not in wait mode, the slow mode divider is off and the bus clock’s frequency is not changed.
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Clock Registers 10.7 Clock Registers This section describes the clock registers. All register addresses shown reflect the reset state. Registers may be mapped to any 2-Kbyte space. 10.7.1 Slow Mode Divider Register Address: $00E0 Read: Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 Write: Reset: 2 1 Bit 0 SLDV2 SLDV1 SLDV0 0 0 0 = Unimplemented Figure 10-5.
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Clock Generation Module (CGM) 10.7.2 Real-Time Interrupt Control Register Address: $0014 Bit 7 Read: RTIE Write: Reset: 0 6 5 RSWAI RSBCK 0 0 = Unimplemented 4 0 0 3 2 1 Bit 0 RTBYP RTR2 RTR1 RTR0 0 0 0 0 Figure 10-6. Real-Time Interrupt Control Register (RTICTL) Read: Anytime Write: Varies on a bit-by-bit basis RTIE — Real-Time Interrupt Enable Bit Write anytime. 0 = Interrupt requests from RTI are disabled. 1 = Interrupt is requested when RTI is set.
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Clock Registers 10.7.3 Real-Time Interrupt Flag Register Address: $0015 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 RTIF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-7. Real-Time Interrupt Flag Register (RTIFLG) RTIF — Real-Time Interrupt Flag Bit This bit is cleared automatically by a write to this register with this bit set. 0 = Timeout has not yet occurred. 1 = Set when the timeout period is met 10.7.
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Clock Generation Module (CGM) FCOP — Force COP Watchdog Reset Bit Writes are not allowed in normal modes; can be written anytime in special modes. If DISR is set, this bit has no effect. 0 = Normal operation 1 = Force a COP reset, if COP is enabled. DISR — Disable Resets from COP Watchdog and Clock Monitor Bit Writes are not allowed in normal modes, anytime in special modes. 0 = Normal operation 1 = Regardless of other control bit states, COP and clock monitor do not generate a system reset.
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Clock Divider Chains 10.
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Clock Generation Module (CGM) P CLOCK TEN REGISTER: TMSK2 BITS: PR2, PR1, AND PR0 0:0:0 REGISTER: PACTL BITS: PAEN, CLK1, AND CLK0 0:x:x ÷2 0:0:1 1:0:0 ÷2 0:1:0 1:0:1 ÷2 0:1:1 1:1:0 PACLK/256 PULSE ACC LOW BYTE ÷2 1:1:1 1:0:0 PACLK/65536 (PAOV) ÷2 1:0:1 ÷2 PULSE ACC HIGH BYTE PACLK GATE LOGIC PAMOD PORT T7 TO TIM COUNTER PAEN Figure 10-11.
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Clock Divider Chains P CLOCK 5-BIT MODULUS COUNTER (PR0-PR4) ÷2 ÷2 TO ATD REGISTER: SP0BR BITS: SPR2, SPR1, AND SPR0 0:0:0 SPI BIT RATE ÷2 0:0:1 ÷2 0:1:0 ÷2 0:1:1 BDM BIT CLOCK: E CLOCK ÷2 1:0:0 SYNCHRONIZER ÷2 1:0:1 ÷2 1:1:0 ÷2 1:1:1 BKGD IN BKGD DIRECTION BKGD PIN LOGIC BKGD OUT Receive: Detect falling edge, count 12 E clocks, sample input Transmit 1: Detect falling edge, count 6 E clocks while output is high impedance, drive out 1 E cycle pulse high, high-impedance output again T
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Clock Generation Module (CGM) M68HC12B Family Data Sheet, Rev. 9.
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Chapter 11 Pulse-Width Modulator (PWM) 11.1 Introduction The pulse-width modulator (PWM) subsystem provides four independent 8-bit PWM waveforms or two 16-bit PWM waveforms or a combination of one 16-bit and two 8-bit PWM waveforms. Each waveform channel has a programmable period and a programmable duty cycle as well as a dedicated counter. A flexible clock select scheme allows four different clock sources to be used with the counters.
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Pulse-Width Modulator (PWM) CLOCK SOURCE (ECLK) CENTR = 0 FROM PORT P DATA REGISTER PWCNTx GATE UP COUNTER ONLY CLOCK EDGE SYNC RESET 8-BIT COMPARE PWDTYx S Q MUX MUX Q 8-BIT COMPARE = TO PIN DRIVER R PWPERx PPOLx PWENx PPOL = 0 PPOL = 1 PWDTY PWPER Figure 11-1.
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Introduction PSBCK PSBCK IS BIT 0 OF PWCTL REGISTER. INTERNAL SIGNAL LIMBDM IS 1 IF THE MCU IS IN BACKGROUND DEBUG MODE.
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Pulse-Width Modulator (PWM) 11.2 PWM Register Descriptions This section provides descriptions of the PWM registers. 11.2.1 PWM Clocks and Concatenate Register Address: $0040 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0 0 0 0 0 0 0 0 0 Reset: Figure 11-4.
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PWM Register Descriptions 11.2.2 PWM Clock Select and Polarity Register Address: $0041 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0 0 0 0 0 0 0 0 0 Figure 11-5. PWM Clock Select and Polarity Register (PWPOL) Read: Anytime Write: Anytime PCLK3 — PWM Channel 3 Clock Select Bit 0 = Clock B is the clock source for channel 3. 1 = Clock S1 is the clock source for channel 3.
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Pulse-Width Modulator (PWM) 11.2.3 PWM Enable Register Address: $0042 Read: Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 PWEN3 PWEN2 PWEN1 PWEN0 0 0 0 0 = Unimplemented Figure 11-6. PWM Enable Register (PWEN) Read: Anytime Write: Anytime Setting any of the PWENx bits causes the associated port P line to become an output regardless of the state of the associated data direction register (DDRP) bit. This does not change the state of the data direction bit.
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PWM Register Descriptions 11.2.4 PWM Prescale Counter Address: $0043 Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 = Unimplemented Figure 11-7. PWM Prescale Counter (PWPRES) Read: Anytime Write: Only in special mode (SMOD = 1) PWPRES is a free-running 7-bit counter. 11.2.
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Pulse-Width Modulator (PWM) 11.2.7 PWM Scale Register 1 Address: $0046 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 11-10. PWM Scale Register 1 (PWSCAL1) Read: Anytime Write: Anytime A write causes the scaler counter PWSCNT1 to load the PWSCAL1 value unless it is in special mode with DISCAL = 1 in the PWTST register.
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PWM Register Descriptions 11.2.9 PWM Channel Counters 0–3 Address: $0048 Bit 7 Read: Bit 7 Write: Reset: 0 6 5 4 3 2 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 Figure 11-12. PWM Channel Counter 0 (PWCNT0) Address: $0049 Bit 7 Read: Bit 7 Write: Reset: 0 6 5 4 3 2 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 Figure 11-13.
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Pulse-Width Modulator (PWM) 11.2.10 PWM Channel Period Registers 0–3 Address: $004C Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Figure 11-16. PWM Channel Period Register 0 (PWPER0) Address: $004D Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Figure 11-17.
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PWM Register Descriptions 11.2.11 PWM Channel Duty Registers 0–3 Address: $0050 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Figure 11-20. PWM Channel Duty Register 0 (PWDTY0) Address: $0051 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Figure 11-21.
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Pulse-Width Modulator (PWM) 11.2.12 PWM Control Register Address: $0054 Read: Bit 7 6 5 0 0 0 0 0 0 Write: Reset: 4 3 2 1 Bit 0 PSWAI CENTR RDPP PUPP PSBCK 0 0 0 0 0 = Unimplemented Figure 11-24. PWM Control Register (PWCTL) Read: Anytime Write: Anytime PSWAI — PWM Halts While in Wait Mode Bit 0 = Continue PWM main clock generator while in wait mode. 1 = Halt PWM main clock generator when the part is in wait mode.
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PWM Register Descriptions 11.2.13 PWM Special Mode Register Address: $0055 Bit 7 Read: Write: Reset: DISCR 6 5 DISCP DISCAL 0 0 0 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 11-25. PWM Special Mode Register (PWTST) Read: Anytime Write: Only in special mode (SMODN = 0) These bits are available only in special mode and are reset in normal mode.
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Pulse-Width Modulator (PWM) 11.2.15 Port P Data Direction Register Address: $0057 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0 0 0 0 0 0 0 0 0 Figure 11-27. Port P Data Direction Register (DDRP) Read: Anytime Write: Anytime DDRP determines pin direction of port P when used for general-purpose I/O. When cleared, I/O pin is configured for input. When set, I/O pin is configured for output. 11.
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Using the Output Compare 7 Feature to Generate a PWM 11.4.1 PWM Period Calculation These parameters were used to calculate the high-time values shown in Table 11-3: • Period = $1000 (Hex) = 4096 (decimal) • E clock = 8 MHz • Prescaler = 4 • Frequency = (8 MHz) / (#clocks_count*prescaler) = (8 MHz) (4096*4) = 500 Hz • If period ($4096 Clocks) => frequency = 500 Hz Table 11-3. PWM Period Calculations High-Time Values Duty Cycle HEX Count Decimal Count $0020 32 0% $0040 64 1.5% $0080 128 3.
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Pulse-Width Modulator (PWM) 11.4.3 Code Listing NOTE A comment line is deliminted by a semi-colon. If there is no code before comment, an “;” must be placed in the first column to avoid assembly errors. INCLUDE 'EQUATES.
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Chapter 12 Standard Timer (TIM) 12.1 Introduction The standard timer module (TIM) for the MC68HC912B32 and MC68HC(9)12BC32 consists of a 16-bit software-programmable counter driven by a prescaler. It contains eight complete 16-bit input capture/output compare channels and one 16-bit pulse accumulator. See Figure 12-2. The MC68HC12BE32 contains an enhanced capture timer (ECT). The timer on the MC68HC12BE32 is backward compatible with code used on the MC68HC912B32.
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Standard Timer (TIM) 12.
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Block Diagram 12.3.1 Timer Compare Force Register Address: $0081 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0 0 0 0 0 0 0 0 Figure 12-3.
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Standard Timer (TIM) 12.3.4 Timer Count Register Address: $0084 Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: Address: $0085 Read: Write: Reset: = Unimplemented Figure 12-6.
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Block Diagram TSBCK — Timer Stops While in Background Mode Bit 0 = Allows timer to continue running while in background mode 1 = Disables timer when MCU is in background mode; useful for emulation TFFCA — Timer Fast Flag Clear All Bit 0 = Allows timer flag clearing to function normally 1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel ($90–$9F) causes the corresponding channel flag, CnF, to be cleared.
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Standard Timer (TIM) Address: $008A Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 Reset: Figure 12-10. Timer Control Register 3 (TCTL3) Address: $008B Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 Reset: Figure 12-11.
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Block Diagram C7I–C0I — Input Capture/Output Compare x Interrupt Enable Bits Address: $008D Bit 7 Read: Write: Reset: TOI 0 6 0 5 4 3 2 1 Bit 0 PUPT RDPT TCRE PR2 PR1 PR0 0 0 0 0 0 0 0 = Unimplemented Figure 12-13.
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Standard Timer (TIM) 12.3.8 Timer Interrupt Flag Registers Address: $008E Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 Figure 12-14. Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism; set bits cause corresponding bits to be cleared TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a 1 to the bit.
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Block Diagram 12.3.9 Timer Input Capture/Output Compare Registers Address: $0090 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Address: $0091 Read: Write: Reset: Figure 12-16.
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Standard Timer (TIM) Address: $0096 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Address: $0097 Read: Write: Reset: Figure 12-19.
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Block Diagram Address: $009C Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Address: $009D Read: Write: Reset: Figure 12-22.
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Standard Timer (TIM) PAEN — Pulse Accumulator System Enable Bit 0 = Pulse accumulator system disabled 1 = Pulse accumulator system enabled PAEN is independent from TEN. PAMOD — Pulse Accumulator Mode Bit 0 = Event counter mode 1 = Gated time accumulation mode PEDGE — Pulse Accumulator Edge Control Bit For PAMOD = 0 (event counter mode) 0 = Falling edges on the pulse accumulator input pin (PT7/PAI) cause the count to be incremented.
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Block Diagram 12.3.11 Pulse Accumulator Flag Register Address: $00A1 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 PAOVF PAIF 0 0 0 0 0 0 0 0 Figure 12-25. Pulse Accumulator Flag Register (PAFLG) Read: Anytime Write: Anytime When the TFFCA bit in the TSCR register is set, any access to the PACNT register clears all the flags in the PAFLG register. PAOVF — Pulse Accumulator Overflow Flag Set when the 16-bit pulse accumulator overflows from $FFFF to $0000.
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Standard Timer (TIM) 12.3.13 Timer Test Register Address: $00AD Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 TCBYP PCBYP 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-27. Timer Test Register (TIMTST) Read: Anytime Write: Only in special mode (SMODN = 0) TCBYP — Timer Divider Chain Bypass Bit 0 = Normal operation 1 = 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is bypassed. The clock drives both halves directly.
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Timer Operation in Modes 12.3.15 Data Direction Register for Timer Port Address: $00AF Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0 0 0 0 0 0 0 0 0 Figure 12-29.
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Standard Timer (TIM) 12.5 Using the Output Compare Function to Generate a Square Wave This timer exercise is intended to utilize the output compare function to generate a square wave of predetermined duty cycle and frequency. Square wave frequency 1000 Hz, duty cycle 50% The program generates a square wave, 50 percent duty cycle, on output compare 2 (OC2). The signal will be measured by the HC11 on the UDLP1 board. It assumes a 8.0 MHz operating frequency for the E clock.
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Using the Output Compare Function to Generate a Square Wave ---------------------------------------------------------------------; MAIN PROGRAM ; ---------------------------------------------------------------------ORG $7000 ; 16K On-Board RAM, User code data area, ; ; start main program at $7000 MAIN: BSR TIMERINIT ; Subroutine used to initialize the timer: ; ; Output compare channel, no interrupts BSR SQWAVE ; Subroutine to generate square wave DONE: BRA DONE ; Branch to itself, Convinient for Breakpoint
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Standard Timer (TIM) M68HC12B Family Data Sheet, Rev. 9.
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Chapter 13 Enhanced Capture Timer (ECT) Module 13.1 Introduction The M68HC12 enhanced capture timer (ECT) module has the features of the M68HC12 standard timer (TIM) module enhanced by additional features in order to enlarge the field of applications.
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Enhanced Capture Timer (ECT) Module The 16-bit modulus down-counter can control the transfer of the IC register’s contents and the pulse accumulators to the respective holding registers for a given period, every time the count reaches 0. The modulus down-counter can also be used as a stand-alone timebase with periodic interrupt capability. 13.3.1 IC Channels The IC channels are composed of four standard IC registers and four buffered IC channels.
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Enhanced Capture Timer Modes of Operation ÷ 1, 2, ...
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Enhanced Capture Timer (ECT) Module ÷1, 2, ...
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Timer Registers 13.3.2 Pulse Accumulators Four 8-bit pulse accumulators with four 8-bit holding registers are associated with the four IC buffered channels. See Figure 13-3. A pulse accumulator counts the number of active edges at the input of its channel. The user can prevent 8-bit pulse accumulators from counting further than $FF by PACMX control bit in input control system control register (ICSYS). In this case, a value of $FF means that 255 counts or more have occurred.
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Enhanced Capture Timer (ECT) Module LOAD HOLDING REGISTER AND RESET PULSE ACCUMULATOR 0 EDG0 PT0 EDGE DETECTOR 8-BIT PAC0 (PACN0) DELAY COUNTER PA0H HOLDING REGISTER INTERRUPT 0 EDG1 PT1 EDGE DETECTOR 8-BIT PAC1 (PACN1) DELAY COUNTER HOST CPU DATA BUS PA1H HOLDING REGISTER 0 EDG2 PT2 EDGE DETECTOR 8-BIT PAC2 (PACN2) DELAY COUNTER PA2H HOLDING REGISTER INTERRUPT 0 EDG3 PT3 EDGE DETECTOR 8-BIT PAC3 (PACN3) DELAY COUNTER PA3H HOLDING REGISTER Figure 13-3.
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Timer Registers TIMCLK (TIMER CLOCK) CLK1 CLK0 CLOCK SELECT (PAMOD) EDGE DETECTOR PT7 PACLK PACLK / 256 PACLK / 65536 PRESCALED CLOCK FROM TIMER 4:1 MUX INTERRUPT 8-BIT PAC3 (PACN3) 8-BIT PAC2 (PACN2) MUX INTERMODULE BUS PACA DIVIDE BY 64 M CLOCK INTERRUPT 8-BIT PAC1 (PACN1) 8-BIT PAC0 (PACN0) DELAY COUNTER PACB EDGE DETECTOR PT0 Figure 13-4. 16-Bit Pulse Accumulators Block Diagram M68HC12B Family Data Sheet, Rev. 9.
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Enhanced Capture Timer (ECT) Module 13.4.1 Timer Input Capture/Output Compare Select Register Address: $0080 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 0 0 0 0 0 0 0 Figure 13-5. Timer Input Capture/Output Compare Select Register (TIOS) Read: Anytime Write: Anytime IOS[7:0] — Input Capture or Output Compare Channel Configuration Bits 0 = The corresponding channel acts as an input capture.
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Timer Registers OC7M[7:0] Bits The bits of OC7M correspond bit-for-bit with the timer port (PORTT) bits. Setting the OC7Mn will set the corresponding port to be an output port regardless of the state of the DDRTn bit, when the corresponding TIOSn bit is set to be an output compare. This does not change the state of the DDRT bits. At successful OC7, for each bit that is set in OC7M, the corresponding data bit OC7D is stored to the corresponding bit of the timer port. See Figure 13-8.
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Enhanced Capture Timer (ECT) Module 13.4.5 Timer Count Registers Address: $0084 Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Write: Reset: Address: $0085 Read: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 13-10.
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Timer Registers TSWAI — Timer Module Stops While in Wait Bit TSWAI also affects pulse accumulators and modulus down counters. 0 = Allows the timer module to continue running during wait 1 = Disables the timer module when the MCU is in wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSBCK — Timer and Modulus Counter Stop While in Background Mode Bit TBSCK does not stop the pulse accumulator.
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Enhanced Capture Timer (ECT) Module Table 13-1. Compare Result Output Action OMn OLn Action 0 0 Timer disconnected from output pin logic 0 1 Toggle OCn output line 1 0 Clear OCn output line to 0 1 1 Set OCn output line to 1 To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output compare 7 and 0, respectively, the user must set the corresponding bits IOSn = 1, OMn = 0, and OLn = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
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Timer Registers 13.4.8 Timer Interrupt Mask Registers Address: $008C Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 0 0 Figure 13-16. Timer Interrupt Mask 1 Register (TMSK1) Read: Anytime Write: Anytime C7I–C0I — Input Capture/Output Compare x Interrupt Enable Bits The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt.
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Enhanced Capture Timer (ECT) Module PR2, PR1, and PR0 — Timer Prescaler Select Bits These three bits specify the number of ÷2 stages that are to be inserted between the module clock and the main timer counter. See Table 13-3. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal 0. Table 13-3.
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Timer Registers 16-BIT MAIN TIMER PTN DELAY COUNTER EDGE DETECTOR SET CNF INTERRUPT TCN INPUT CAPTURE REGISTER BUFEN • LATQ • TFMOD TCNH IC HOLDING REGISTER Figure 13-19. C3F–C0F Interrupt Flag Setting Address: $008F Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 TOF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13-20. Main Timer Interrupt Flag 2 (TFLG2) Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
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Enhanced Capture Timer (ECT) Module Address: $0092–$0093 Read: Write: Reset: Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 13-22.
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Timer Registers Address: $009A–$009B Read: Write: Reset: Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 13-26.
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Enhanced Capture Timer (ECT) Module 13.4.11 16-Bit Pulse Accumulator A Control Register Address: $00A0 Bit 7 Read: 0 Write: Reset: 6 5 4 3 2 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 0 = Unimplemented Figure 13-29. 16-Bit Pulse Accumulator A Control Register (PACTL) Read: Anytime Write: Anytime Sixteen-bit pulse accumulator A (PACA) is formed by cascading the 8-bit pulse accumulators PAC3 and PAC2. When PAEN is set, the PACA is enabled.
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Timer Registers CLK1 and CLK0 — Clock Select Bits CLK1 CLK0 Clock Source 0 0 Use timer prescaler clock as timer counter clock 0 1 Use PACLK as input to timer counter clock 1 0 Use PACLK/256 as timer counter clock frequency 1 1 Use PACLK/65,536 as timer counter clock frequency If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter.
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Enhanced Capture Timer (ECT) Module 13.4.13 Pulse Accumulators Count Registers Address: $00A2 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 13-31. Pulse Accumulator Count Register 3 (PACN3) Address: $00A3 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 13-32.
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Timer Registers The two 8-bit pulse accumulators, PAC1 and PAC0, are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN = 1 in PBCTL, $B0) the PACN1 and PACN0 register contents are, respectively, the high and low bytes of the PACB. When PACN1 overflows from $FF to $00, the interrupt flag PBOVF in PBFLG ($B1) is set. Full count register access should take place in one clock cycle.
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Enhanced Capture Timer (ECT) Module MCEN — Modulus Down-Counter Enable Bit When MCEN = 0, the counter is preset to $FFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. 0 = Modulus counter disabled. 1 = Modulus counter is enabled. MCPR1 and MCPR0 — Modulus Counter Prescaler Select Bits These two bits specify the division rate of the modulus counter prescaler.
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Timer Registers 13.4.16 Input Control Pulse Accumulators Control Register Address: $00A8 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 PA3EN PA2EN PA1EN PA0EN 0 0 0 0 0 0 0 0 Figure 13-37. Input Control Pulse Accumulators Control Register (ICPACR) Read: Anytime Write: Anytime The 8-bit pulse accumulators, PAC3 and PAC2, can be enabled only if PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN have no effect.
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Enhanced Capture Timer (ECT) Module 13.4.18 Input Control Overwrite Register Address: $00AA Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 0 0 0 0 0 0 0 0 Figure 13-39. Input Control Overwrite Register (ICOVW) Read: Anytime Write: Anytime An IC register is empty when it has been read or latched into the holding register. A holding register is empty when it has been read.
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Timer Registers By setting TFMOD in queue mode, when NOVW bit is set and the corresponding capture and holding registers are emptied, an input capture event will first update the related input capture register with the main timer contents. At the next event, the TCn data is transferred to the TCnH register, the TCn is updated, and the CnF interrupt flag is set. See Figure 13-19. In all other input capture cases, the interrupt flag is set by a valid external event on PTn.
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Enhanced Capture Timer (ECT) Module TCBYP — Main Timer Divider Chain Bypass Bit 0 = Normal operation 1 = For testing only. The 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is bypassed. The clock drives both halves directly. When the high byte of timer counter TCNT ($84) overflows from $FF to $00, the TOF flag in TFLG2 ($8F) will be set. 13.4.
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Timer Registers DDT[7:0] — Data Direction Bits for Timer Port The timer forces the I/O state to be an output for each timer port line associated with an enabled output compare. In these cases the data direction bits will not be changed, but have no effect on the direction of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. Input captures do not override the DDRT settings.
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Enhanced Capture Timer (ECT) Module PBOVF — Pulse Accumulator B Overflow Flag This bit is set when the 16-bit pulse accumulator B overflows from $FFFF to $0000 or when 8-bit pulse accumulator 1 (PAC1) overflows from $FF to $00. This bit is cleared by a write to the PBFLG register with bit 1 set. Any access to the PACN1 and PACN0 registers will clear the PBOVF flag in this register when TFFCA bit in register TSCR ($86) is set. 13.4.
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Timer Registers 13.4.26 Modulus Down-Counter Count Registers Address: $00B6 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 Address: $00B7 Read: Write: Reset: Figure 13-50.
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Enhanced Capture Timer (ECT) Module Address: $00BA Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Address: $00BB Read: Write: Reset: Figure 13-52.
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Timer and Modulus Counter Operation in Different Modes 13.5 Timer and Modulus Counter Operation in Different Modes STOP Timer and modulus counter are off since clocks are stopped. BGDM Timer and modulus counter keep on running unless bit 5, TSBCK, of TSCR is set to 1. See 13.4.6 Timer System Control Register. WAIT Counters keep on running, unless the TSWAI bit in TSCR is set to 1. See 13.4.6 Timer System Control Register.
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Enhanced Capture Timer (ECT) Module M68HC12B Family Data Sheet, Rev. 9.
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Chapter 14 Serial Interface 14.1 Introduction • • • The serial interface of the MCU consists of two independent serial input/output (I/O) subsystems: Serial communication interface (SCI) Serial peripheral interface (SPI) Each serial pin shares function with the general-purpose port pins of port S. The SCI is an NRZ (non-return to zero) type system that is compatible with standard RS-232 systems.
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Serial Interface 14.2 Serial Communication Interface (SCI) The SCI on the MCU is an NRZ format (one start, eight or nine data, and one stop bit) asynchronous communication system with independent internal baud rate generation circuitry and an SCI transmitter and receiver. It can be configured for eight or nine data bits (one of which may be designated as a parity bit, odd or even). If enabled, parity is generated in hardware for transmitted and received data. Receiver parity errors are flagged in hardware.
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Serial Communication Interface (SCI) 14.2.
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Serial Interface 14.2.3 SCI Register Descriptions Control and data registers for the SCI subsystem are described here. The memory address indicated for each register is the default address that is in use after reset. The entire 512-byte register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space. 14.2.3.
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Serial Communication Interface (SCI) 14.2.3.2 SCI Control Register 1 Address: Read: Write: Reset: $00C2 Bit 7 6 5 4 3 2 1 Bit 0 LOOPS WOMS RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 Figure 14-5. SCI Control Register 1 (SC0CR1) Read: Anytime Write: Anytime LOOPS — SCI LOOP Mode/Single-Wire Mode Enable Bit 0 = SCI transmit and receive sections operate normally. 1 = SCI receive section is disconnected from the RXD pin and the RXD pin is available as general-purpose I/O.
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Serial Interface RSRC — Receiver Source Bit When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver.
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Serial Communication Interface (SCI) 14.2.3.3 SCI Control Register 2 Address: Read: Write: Reset: $00C3 Bit 7 6 5 4 3 2 1 Bit 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 14-6.
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Serial Interface 14.2.3.4 SCI Status Register 1 Address: Read: $00C4 Bit 7 6 5 4 3 2 1 Bit 0 TDRE TC RDRF IDLE OR NF FE PF 1 1 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 14-7. SCI Status Register 1 (SC0SR1) Read: Anytime; used in auto clearing mechanism Write: Has no meaning or effect The bits in these registers are set by various conditions in the SCI hardware and are cleared automatically by special acknowledge sequences.
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Serial Communication Interface (SCI) OR — Overrun Error Flag New byte is ready to be transferred from the receive shift register to the receive data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit is cleared. 0 = No overrun 1 = Overrun detected NF — Noise Error Flag Set during the same cycle as the RDRF bit but not set in the case of an overrun (OR).
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Serial Interface 14.2.3.6 SCI Data Register Address: Read: Write: Reset: $00C6 Bit 7 R8 U 6 T8 5 0 U 0 = Unimplemented 4 0 0 U = Unaffected 3 0 2 0 1 0 Bit 0 0 0 0 0 0 Figure 14-9. SCI Data Register High (SC0DRH) Address: Read: Write: Reset: $00C7 Bit 7 6 5 4 3 2 1 Bit 0 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Unaffected by reset Figure 14-10. SCI Data Register Low (SC0DRL) Read: Anytime Write: Varies on a bit by bit basis R8 — Receive Bit 8 Write has no meaning or effect.
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Serial Peripheral Interface (SPI) 14.3 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MCU to communicate synchronously with peripheral devices and other microprocessors. The SPI system in the MCU can operate as a master or as a slave. The SPI is also capable of interprocessor communications in a multiple master system. When the SPI is enabled, all pins that are defined by the configuration as inputs will be inputs regardless of the state of the DDRS bits for those pins.
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Serial Interface 14.3.1 SPI Baud Rate Generation The P clock is input to a divider series and the resulting SPI clock rate may be selected to be P divided by 2, 4, 8, 16, 32, 64, 128, or 256. Three bits in the SP0BR register control the SPI clock rate. This baud rate generator is activated only when SPI is in the master mode and serial transfer is taking place. Otherwise, this divider is disabled to save power. 14.3.
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Serial Peripheral Interface (SPI) TRANSFER BEGIN END SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE I MOSI/MISO CHANGE O MOSI PIN CHANGE O MISO PIN SEL SS (O) MASTER ONLY SEL SS (I) tL MSB first (LSBF= 0) : LSB first (LSBF = 1) : tT MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB tL tI Minimum 1/2 SCK for tT, tl, tL Figure 14-13. SPI Clock Format 1 (CPHA = 1) 14.3.
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Serial Interface 14.3.4 Bidirectional Mode (MOMI or SISO) In bidirectional mode, the SPI uses only one serial data pin for external device interface. The MSTR bit decides which pin to be used. The MOSI pin becomes a serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes a serial data I/O (SISO) pin for the slave mode. The direction of each serial I/O pin depends on the corresponding DDRS bit.
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Serial Peripheral Interface (SPI) SPE — SPI System Enable Bit 0 = SPI internal hardware is initialized and SPI system is in a low-power disabled state. 1 = PS4–PS7 are dedicated to the SPI function. When MODF is set, SPE always reads 0. SP0CR1 must be written as part of a mode fault recovery sequence. SWOM — Port S Wired-OR Mode Bit Controls not only SPI output pins but also the general-purpose output pins (PS4–PS7) which are not used by SPI. 0 = SPI and/or PS4–PS7 output buffers operate normally.
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Serial Interface SPC0 — Serial Pin Control 0 Bit This bit decides serial pin configurations with MSTR control bit. Table 14-4. Serial Pin Control SPC0(1) Pin Mode MSTR MISO(2) MOSI(3) SCK(4) SS(5) 0 Slave out Slave in SCK in SS in 1 Master in Master out SCK out SS I/O 0 Slave I/O General-purposeI/O SCK in SS in 1 General-purposeI/O Master I/O SCK out SS I/O #1 Normal 0 #2 #3 Bidirectional 1 #4 1. The serial pin control 0 bit enables bidirectional configurations. 2.
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Serial Peripheral Interface (SPI) 14.3.5.4 SPI Status Register Address: $00D3 Bit 7 6 5 4 3 2 1 Bit 0 Read: SPIF WCOL 0 MODF 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 14-18.
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Serial Interface form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the SCK clock from the master so the data is exchanged effectively between the master and the slave. NOTE Some slave devices are simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. 14.
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Port S DDS0 — Data Direction for Port S Bit 0 If the SCI receiver is configured for 2-wire SCI operation, corresponding port S pins are input regardless of the state of these bits. DDS1 — Data Direction for Port S Bit 1 If the SCI transmitter is configured for 2-wire SCI operation, corresponding port S pins are output regardless of the state of these bits. DDS2 and DDS3 — Data Direction for Port S Bit 2 and Bit 3 These bits are for general-purpose only.
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Serial Interface PUPS1 — Pullup Port S Enable PS3 and PS2 Bit 0 = No internal pullups on port S bits 3 and 2 1 = Port S input pins for bits 3 and 2 have an active pullup device. If a pin is programmed as output, the pullup device becomes inactive. PUPS0 — Pullup Port S Enable PS1 and PS0 Bit 0 = No internal pullups on port S bits 1 and 0 1 = Port S input pins for bits 1 and 0 have an active pullup device. If a pin is programmed as output, the pullup device becomes inactive. 14.
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Synchronous Character Transmission using the SPI MOVB #$08,SC1CR2 ; Set for No Ints, and Transmitter enabled(SC1CR2) LDAA STD SC1SR1 SC1DRH ; 1st step to clear TDRE flag: Read SC1SR1 ; 2nd step to clear TDRE flag: Write SC1DR register LDX #DATA ; Use X as a pointer to DATA.
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Serial Interface INCLUDE 'EQUATES.
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Chapter 15 Byte Data Link Communications (BDLC) 15.1 Introduction The byte data link communications module (BDLC) provides access to an external serial communication multiplex bus, operating according to the SAE J1850 protocol. 15.2 Features Features of the BDLC module include: • SAE J1850 Class B Data Communications Network Interface compatible and ISO compatible for low-speed (<125 Kbps) serial data communications in automotive applications • 10.
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Byte Data Link Communications (BDLC) TO CPU CPU INTERFACE PROTOCOL HANDLER MUX INTERFACE PHYSICAL INTERFACE BDLC TO J1850 BUS Figure 15-1. BDLC Block Diagram 15.4 BDLC Operating Modes The BDLC has five main modes of operation which interact with the power supplies, pins, and rest of the MCU as shown in Figure 15-2.
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Power-Conserving Modes 15.4.1 Power Off Mode For guaranteed BDLC operation, this mode is entered from reset mode when the BDLC supply voltage, VDD, drops below its minimum specified value. The BDLC is placed in reset mode by low-voltage reset (LVR) before being powered down. In power off mode, the pin input and output specifications are not guaranteed. 15.4.
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Byte Data Link Communications (BDLC) To disengage a BDLC node from receiving J1850 traffic: • Verify all BSVR flags are clear. • Do not load the BDR. • Set the ALOOP bit (after placing the analog transceiver into loopback mode) or DLOOP bit in BCR2. The BDLC can then be put into wait mode or stop mode and does not wake up with J1850 traffic.
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Loopback Modes 15.5.3 BDLC Stop and CPU Stop Mode This power-conserving mode is entered automatically from run mode when the WCM bit in the BCR1 register is set followed by a CPU STOP instruction. This is the lowest-power mode that the BDLC can enter. In this mode: • The BDLC internal clocks are stopped. • The CPU internal clocks are stopped. • The BDLC awaits J1850 network activity.
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Byte Data Link Communications (BDLC) 15.7 BDLC MUX Interface The MUX (multiplex) interface is responsible for bit encoding/decoding and digital noise filtering between the protocol handler and the physical interface. 15.7.1 Rx Digital Filter The receiver section of the BDLC includes a digital low-pass filter to remove narrow noise pulses from the incoming message. An outline of the digital filter is shown in Figure 15-3.
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BDLC MUX Interface 15.7.1.2 Performance The performance of the digital filter is best described in the time domain rather than the frequency domain. If the signal on the BDRxD signal transitions, there is a delay before that transition appears at the filtered Rx data output signal. This delay is between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points. This filter delay must be taken into account when performing message arbitration.
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Byte Data Link Communications (BDLC) 15.7.2.2 Data — In-Message Data Bytes The data bytes contained in the message include the message priority/type, message ID byte (typically, the physical address of the responder), and any actual data being transmitted to the receiving node. The message format used by the BDLC is similar to the 3-byte consolidated header message format outlined by the SAE J1850 document.
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BDLC MUX Interface When the last byte of a message has been transmitted onto the J1850 bus and the EOF symbol time has expired, all nodes then must wait for the IFS symbol time to expire before transmitting a start-of-frame (SOF) symbol, marking the beginning of another message. However, if the BDLC is waiting for the IFS period to expire before beginning a transmission and a rising edge is detected before the IFS time has expired, it synchronizes internally to that edge.
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Byte Data Link Communications (BDLC) ACTIVE 128 µs OR 64 µs OR 64 µs PASSIVE (A) LOGIC 0 ACTIVE 128 µs PASSIVE (B) LOGIC 1 ACTIVE 200 µs ≥ 240 µs 200 µs PASSIVE (D) START OF FRAME (C) BREAK (E) END OF DATA 300 µs ACTIVE 280 µs 20 µs IDLE > 300 µs PASSIVE (F) END OF FRAME (G) INTER-FRAME SEPARATION (H) IDLE Figure 15-5. J1850 VPW Symbols with Nominal Symbol Times 15.7.3.
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BDLC MUX Interface 15.7.3.5 Start-of-Frame Symbol (SOF) The SOF symbol is defined as passive-to-active transition followed by an active period 200 µs in length (see Figure 15-5(D)). This allows the data bytes which follow the SOF symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. 15.7.3.6 End-of-Data Symbol (EOD) The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 µs in length (see Figure 15-5(E)). 15.7.3.
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Byte Data Link Communications (BDLC) 200 µs 128 µs 64 µs ACTIVE (1) INVALID PASSIVE BIT PASSIVE A ACTIVE (2) VALID PASSIVE LOGIC 0 PASSIVE A B ACTIVE (3) VALID PASSIVE LOGIC 1 PASSIVE B C ACTIVE (4) VALID EOD SYMBOL PASSIVE C D Figure 15-6. J1850 VPW Received Passive Symbol Times 15.7.4.1 Invalid Passive Bit See Figure 15-6(1).
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BDLC MUX Interface 300 µs 280 µs ACTIVE (1) VALID EOF SYMBOL PASSIVE A B ACTIVE (2) VALID EOF+ IFS SYMBOL PASSIVE C D Figure 15-7. VPW Received Passive EOF and IFS Symbol Times 15.7.4.5 Valid EOF and IFS Symbols In Figure 15-7(1), if the passive-to-active received transition beginning the SOF symbol of the next message occurs between A and B, the current symbol is considered a valid end-of-frame (EOF) symbol. See Figure 15-7(2).
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Byte Data Link Communications (BDLC) 200 µs 128 µs 64 µs ACTIVE (1) INVALID ACTIVE BIT PASSIVE A ACTIVE (2) VALID ACTIVE LOGIC 1 PASSIVE A B ACTIVE (3) VALID ACTIVE LOGIC 0 PASSIVE B C ACTIVE (4) VALID SOF SYMBOL PASSIVE C D Figure 15-8. J1850 VPW Received Active Symbol Times 15.7.4.
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BDLC MUX Interface 240 µs ACTIVE (2) VALID BREAK SYMBOL PASSIVE E Figure 15-9. J1850 VPW Received BREAK Symbol Times 15.7.4.11 Valid BREAK Symbol In Figure 15-9, if the next active-to-passive received transition does not occur until after E, the current symbol is considered a valid BREAK symbol. A BREAK symbol should be followed by a start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See 15.7.2 J1850 Frame Format for BDLC response to BREAK symbols. 15.7.
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Byte Data Link Communications (BDLC) the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two extra logic 1s do not corrupt the current message. However, if the BDLC has lost arbitration due to noise on the bus, then the two extra logic 1s ensure that the current message is detected and ignored as a noise-corrupted message.
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BDLC Protocol Handler TO PHYSICAL INTERFACE BDTxD BDRxD ALOOP CONTROL BDTxD LOOPBACK MULTIPLEXER RxD DLOOP FROM BCR2 LOOPBACK CONTROL STATE MACHINE Tx SHADOW REGISTER 8 Tx DATA Rx SHADOW REGISTER CONTROL Tx SHIFT REGISTER Rx DATA Rx SHIFT REGISTER 8 TO CPU INTERFACE AND Rx/Tx BUFFERS Figure 15-11. BDLC Protocol Handler Outline Once the Tx shift register has completed its shifting operation for the current byte, the data byte in the Tx shadow register is loaded into the Tx shift register.
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Byte Data Link Communications (BDLC) that contains an indefinite number of data bytes. All other features of the frame remain the same, including the SOF, CRC, and EOD symbols. Another node wishing to send a block mode transmission must first inform all other nodes on the network that this is about to happen. This is usually accomplished by sending a special predefined message. 15.8.5.
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BDLC Registers The BDLC cannot transmit a BREAK symbol. It can receive a BREAK symbol only from the J1850 bus. 15.8.5.5 Summary Table 15-1 provides a bus error summary. Table 15-1. BDLC J1850 Bus Error Summary Error Condition BDLC Function Transmission error For invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt is generated. BDLC stops transmission. Cyclical redundancy check (CRC) error CRC error interrupt is generated. BDLC waits for EOF.
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Byte Data Link Communications (BDLC) CLKS — Clock Select Bit For J1850 bus communications to take place, the nominal BDLC operating frequency (fBDLC) must always be 1.048576 MHz or 1 MHz. The CLKS register bit allows the user to select the frequency (1.048576 MHz or 1 MHz) used to automatically adjust symbol timing. 1 = Binary frequency, 1.
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BDLC Registers 15.9.2 BDLC Control Register 2 Address: $00FA Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 1 1 0 0 0 0 0 0 Figure 15-13. BDLC Control Register 2 (BCR2) This register controls transmitter operations of the BDLC. ALOOP — Analog Loopback Mode Bit This bit determines if the J1850 bus is driven by the analog physical interface’s final drive stage.
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Byte Data Link Communications (BDLC) RX4XE — Receive 4X Enable Bit This bit determines if the BDLC operates at normal transmit and receive speed (10.4 Kbps) or receive only at 41.6 Kbps. This feature is useful for fast downloading data into a J1850 node for diagnostic or factory programming. 1 = BDLC is put in 4X receive-only operation. 0 = BDLC transmits and receives at 10.4 Kbps. Reception of a BREAK symbol automatically clears this bit and sets BDLC state vector register (BSVR) to $001C.
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BDLC Registers TYPE 0 — NO IFR DATA FIELD CRC EOF EOD SOF HEADER CRC TYPE 1 — SINGLE BYTE FROM A SINGLE RESPONDER ID NB ID1 EOD NB EOF EOD NB EOD DATA FIELD EOD SOF HEADER TYPE 2 — SINGLE BYTE FROM MULTIPLE RESPONDERS DATA FIELD CRC IDn EOF EOD SOF HEADER TYPE 3 — MULTIPLE BYTES FROM A SINGLE RESPONDER DATA FIELD CRC IFR DATA FIELD CRC EOF EOD SOF HEADER Figure 15-14. Types of In-Frame Response The BDLC supports the in-frame response (IFR) features of J1850.
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Byte Data Link Communications (BDLC) TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) The TMIFR0 bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a multiple byte IFR without CRC. Response IFR bytes are still subject to J1850 message length maximums (see 15.7.2 J1850 Frame Format and Figure 15-14).
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BDLC Registers If the TMIFR1 bit is set, the BDLC attempts to transmit the normalization symbol followed by the byte in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt (see 15.9.3 BDLC State Vector Register) occurs similar to the main message transmit sequence. The programmer should then load the next byte of the IFR into the BDR for transmission.
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Byte Data Link Communications (BDLC) Table 15-4.
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BDLC Registers The service routines should clear all of the sources that are causing the pending interrupts. Clearing a high priority interrupt may still leave a lower priority interrupt pending, in which case bits I0, I1, and I2 of the BSVR reflect the source of the remaining interrupt request. If fewer states are used or if a different software approach is taken, the jump table can be made smaller or omitted altogether. 15.9.
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Byte Data Link Communications (BDLC) 15.9.5 BDLC Analog Roundtrip Delay Register Address: $00FC Read: Write: Reset: Bit 7 6 ATE RXPOL 1 1 5 4 0 0 0 0 3 2 1 Bit 0 BO3 BO2 BO1 BO0 0 1 1 1 = Unimplemented Figure 15-17. BDLC Analog Roundtrip Delay Register (BARD) Read: Anytime Write: Once in normal modes or anytime in special mode BARD programs the BDLC to compensate for various delays of external transceivers.
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BDLC Registers Table 15-5. Offset Bit Values and Transceiver Delay BO3–BO0 Expected Delay (µs) 0000 9 0001 10 0010 11 0011 12 0100 13 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 15.9.6 Port DLC Control Register Address: $00FD Read: Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 Write: Reset: 2 1 Bit 0 BDLCEN PUPDLC RDPDLC 0 0 0 = Unimplemented Figure 15-18.
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Byte Data Link Communications (BDLC) 15.9.7 Port DLC Data Register Address: $00FE Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 U U U U U U U DLCTX DLCRX Alternate Pin Function: = Unimplemented U = Unaffected Figure 15-19. Port DLC Data Register (PORTDLC) Read: Anytime Write: Anytime This register holds data to be driven out on port DLC pins or data received from port DLC pins.
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Chapter 16 msCAN12 Controller 16.1 Introduction The msCAN12 is the specific implementation of the msCAN concept targeted for the Freescale M68HC12 Family of microcontrollers (MCU). The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the specification from Robert Bosch GmbH dated September 1991.
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msCAN12 Controller CAN STATION 1 CAN STATION 2 ... CAN STATION N CAN SYSTEM msCAN12 CONTROLLER TxCAN RxCAN TRANSCEIVER CAN Figure 16-1. Typical CAN System with msCAN12 16.3.1 Background Modern application layer software is built on two fundamental assumptions: 1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus between two messages.
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Message Storage 16.3.2 Receive Structures The received messages are stored in a 2-stage first-in/first-out (FIFO) input. The two message buffers are mapped into a single memory area (see Figure 16-2). While the background receive buffer (RxBG) is exclusively associated to the msCAN12, the foreground receive buffer (RxFG) is addressable by the CPU12. This scheme simplifies the handler software since only one address area is applicable for the receive process.
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msCAN12 Controller to release the foreground buffer. A new message, which can follow immediately after the IFS field of the CAN frame, is received into RxBG. The over-writing of the background buffer is independent of the identifier filter function. When the msCAN12 module is transmitting, the msCAN12 receives its own messages into the background receive buffer, RxBG, but does not overwrite RxFG, generate a receive interrupt, or acknowledge its own messages on the CAN bus.
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Identifier Acceptance Filter When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message being set up in one of the three transmit buffers. Because messages that are already under transmission cannot be aborted, the user has to request the abort by setting the corresponding abort request flag (ABTRQ) in the transmission control register (CTCR).
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msCAN12 Controller 2. Four identifier acceptance filters, each to be applied to: a. 11 bits of the identifier and the RTR bit of CAN 2.0A messages, or b. 14 most significant bits of the identifier of CAN 2.0B messages Figure 16-4 shows how the first 32-bit filter bank (CIDAR0–CIDAR3, CIDMR0–CIDMR3) produces filter 0 and 1 hit. Similarly, the second filter bank (CIDAR4–CUIDAR7, CIDMR4–CIDMR7) produces filter 2 and three hits.
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Identifier Acceptance Filter ID28 IDR0 ID21 ID20 ID10 IDR0 ID3 ID2 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR IDR1 IDE AC7 CIDMRO AC0 AC7 CIDARO AC0 ID accepted (Filter 0 hit) AC7 CIDMR1 AC0 AC7 CIDAR1 AC0 ID accepted (Filter 1 hit) AC7 CIDMR2 AC0 AC7 CIDAR2 AC0 ID accepted (Filter 2 hit) AC7 CIDMR3 AC0 AC7 CIDAR3 AC0 Figure 16-5. 8-Bit Maskable Acceptance Filters M68HC12B Family Data Sheet, Rev. 9.
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msCAN12 Controller 16.5 Interrupts The msCAN12 supports four interrupt vectors mapped onto 11 different interrupt sources, any of which can be individually masked. For details, see 16.12.5 msCAN12 Receiver Flag Register to 16.12.8 msCAN12 Transmitter Control Register. 1. Transmit interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The empty message buffers TXE flags are set. 2.
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Protocol Violation Protection Table 16-1. msCAN12 Interrupt Vectors Function Wakeup Error interrupts Receive Transmit Source Local Mask WUPIF WUPIE RWRNIF RWRNIE TWRNIF TWRNIE RERRIF RERRIE TERRIF TERRIE BOFFIF BOFFIE OVRIF OVRIE RXF RXFIE TXE0 TXEIE0 TXE1 TXEIE1 TXE2 TXEIE2 Global Mask I bit 16.6 Protocol Violation Protection The msCAN12 will protect the user from accidentally violating the CAN protocol through programming errors.
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msCAN12 Controller Table 16-2. msCAN12 versus CPU Operating Modes CPU Mode msCAN Mode Stop Wait (1) CSWAI = 1 SLPAK = X SFTRES = X CSWAI = X SLPAK = X SFTRES = X Power-down Run Sleep CSWAI = 0 SLPAK = 1 SFTRES = 0 CSWAI = X SLPAK = 1 SFTRES = 0 Soft reset CSWAI = 0 SLPAK = 0 SFTRES = 1 CSWAI = X SLPAK = 0 SFTRES = 1 Normal CSWAI = 0 SLPAK = 0 SFTRES = 0 CSWAI = X SLPAK = 0 SFTRES = 0 1. X means don’t care. 16.7.
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Low-Power Modes The time when the msCAN12 enters sleep mode depends on its activity. For instance, • If it is transmitting, it continues to transmit until there are no more messages to be transmitted and then goes into sleep mode. • If it is receiving, it waits for the end of this message and then goes into sleep mode. • If it is neither transmitting nor receiving, it immediately goes into sleep mode.
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msCAN12 Controller 16.7.3 msCAN12 Power-Down Mode The msCAN12 is in power-down mode when either of these occurs: • CPU is in stop mode. • CPU is in wait mode and the CSWAI bit is set. See 16.12.1 msCAN12 Module Control Register 0 and 16.12.2 msCAN12 Module Control Register 1. When entering power-down mode, the msCAN12 immediately stops all on-going transmissions and receptions, potentially causing CAN protocol violations.
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Clock System CGM MSCAN12 SYSCLK CGMCANCLK CLKSRC EXTALi PRESCALER (1...64) TIME QUANTA CLOCK CLKSRC Figure 16-7. Clocking Scheme The clock source bit (CLKSRC) in the msCAN12 module control register (CMCR1) (see 16.12.3 msCAN12 Bus Timing Register 0) defines whether the msCAN12 is connected to the output of the crystal oscillator (EXTALi) or to a clock twice as fast as the system clock (ECLK). The clock source has to be chosen so that the tight oscillator tolerance requirements (up to 0.
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msCAN12 Controller NRZ SIGNAL SYNC TIME SEGMENT 1 TIME SEG. 2 _SEG PROP_SEG + PHASE_SEG1 (PHASE_SEG2 1 4 ... 16 2 ... 8 8... 25 TIME QUANTA = 1 BIT TIME TRANSMIT POINT SAMPLE POINT (SINGLE OR TRIPLE SAMPLING) Figure 16-8. Segments within the Bit Time Table 16-3. CAN Standard Compliant Bit Time Segment Settings Time Segment 1 TSEG1 Time Segment 2 TSEG2 Synchronize Jump Width SJW 5.. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 ..
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Memory Map 16.10 Memory Map The msCAN12 occupies 128 bytes in the CPU12 memory space. The background receive buffer can be read only in test mode.
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msCAN12 Controller Address(1) Register Name 01x0 IDENTIFIER REGISTER 0 01x1 IDENTIFIER REGISTER 1 01x2 IDENTIFIER REGISTER 2 01x3 IDENTIFIER REGISTER 3 01x4 DATA SEGMENT REGISTER 0 01x5 DATA SEGMENT REGISTER 1 01x6 DATA SEGMENT REGISTER 2 01x7 DATA SEGMENT REGISTER 3 01x8 DATA SEGMENT REGISTER 4 01x9 DATA SEGMENT REGISTER 5 01xA DATA SEGMENT REGISTER 6 01xB DATA SEGMENT REGISTER 7 01xC DATA LENGTH REGISTER 01xD TRANSMIT BUFFER PRIORITY REGISTER(2) 01xE UNUSED 01xF UNUSED 1
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Programmer’s Model of Message Storage Addr.(1) Register Name Read: $01x0 Identifier Register 0 (IDR0) Write: Bit 7 6 5 4 3 2 1 Bit 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 Reset: Read: $01x1 Identifier Register 1 (IDR1) Write: Undefined out of reset ID2 ID1 ID0 Reset: RTR IDE Undefined out of reset Read: $01x2 Identifier Register 2 (IDR2) Write: Reset: Undefined out of reset Read: $01x3 Identifier Register 3 (IDR3) Write: Reset: Undefined out of reset Note 1.
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msCAN12 Controller RTR — Remote Transmission Request Flag This flag reflects the status of the remote transmission request bit in the CAN frame. In case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 = Data frame 1 = Remote frame 16.11.3 Data Length Register The data length register (DLR) keeps the data length field of the CAN frame.
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Programmer’s Model of Message Storage 16.11.4 Data Segment Registers The eight data segment registers (DSR0–DSR7) contain the data to be transmitted or being received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR. Data is transmitted starting from the data segment register 0 (DSR0), beginning with the most significant bit (DB7), and continuing until the number of bytes specified in the data length register (DLR) is complete. Addr.
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msCAN12 Controller PRIO7–PRIO0— Local Priority This field defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the msCAN12 and is defined to be highest for the smallest binary number. The msCAN12 implements this internal prioritization mechanism: – All transmission buffers with a cleared TXE flag participate in the prioritization right before the start of frame (SOF) is sent.
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Programmer’s Model of Control Registers SFTRES — Soft-Reset Bit When this bit is set by the CPU, the msCAN12 immediately enters the soft-reset state. Any on-going transmission or reception is aborted and synchronization to the bus is lost. These registers will go into and stay in the same state as out of hard reset: CMCR0, CRFLG, CRIER, CTFLG, and CTCR. Registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–CIDAR7, and CIDMR0–CIDMR7 can be written only by the CPU when the msCAN12 is in soft-reset state.
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msCAN12 Controller CLKSRC — msCAN12 Clock Source Flag This flag defines which clock source the msCAN12 module is driven from (only for system with CGM module. See 16.9 Clock System and Figure 16-7. 0 = msCAN12 clock source is EXTALi. 1 = msCAN12 clock source is twice the frequency of ECLK. NOTE The CMCR1 register can be written only if the SFTRES bit in CMCR0 is set. 16.12.
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Programmer’s Model of Control Registers 16.12.4 msCAN12 Bus Timing Register 1 Address: $0103 Bit 7 Read: SAMP Write: Reset: 0 6 5 4 3 2 1 Bit 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 0 0 0 Figure 16-19. msCAN12 Bus Timing Register 1 (CBTR1) SAMP — Sampling Bit This bit determines the number of samples of the serial bus to be taken per bit time. If set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule.
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msCAN12 Controller The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 16-8). Presc Þ value BitTime = --------------------------------------- • number Þ of Þ TimeQuanta f CGMCANCLK NOTE The CBTR1 register can be written only if the SFTRES bit in CMCR0 is set. 16.12.5 msCAN12 Receiver Flag Register All bits of this register are read and clear only.
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Programmer’s Model of Control Registers RERRIF — Receiver Error Passive Interrupt Flag This flag is set when the msCAN12 goes into error passive status due to the receive error counter (REC) exceeding 127 and the bus-off interrupt flag is not set(1). If not masked, an error interrupt is pending while this flag is set. 0 = No receiver error passive status has been reached. 1 = msCAN12 went into receiver error passive status.
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msCAN12 Controller 16.12.6 msCAN12 Receiver Interrupt Enable Register Address: $0105 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE 0 0 0 0 0 0 0 0 Figure 16-21. msCAN12 Receiver Interrupt Enable Register (CRIER) WUPIE — Wakeup Interrupt Enable Bit 0 = No interrupt is generated from this event. 1 = A wakeup event results in a wakeup interrupt.
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Programmer’s Model of Control Registers 16.12.7 msCAN12 Transmitter Flag Register The abort acknowledge flags are read only. The transmitter buffer empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. Each transmitter buffer empty flag has an associated interrupt enable bit in the CTCR register. A hard or soft reset resets the register.
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msCAN12 Controller 16.12.8 msCAN12 Transmitter Control Register Address: $0107 Bit 7 Read: 0 Write: Reset: 0 6 5 4 ABTRQ2 ABTRQ1 ABTRQ0 0 0 0 3 0 2 1 Bit 0 TXEIE2 TXEIE1 TXEIE0 0 0 0 0 = Unimplemented Figure 16-23. msCAN12 Transmitter Control Register (CTCR) ABTRQ2–ABTRQ0 — Abort Request Bits The CPU sets an ABTRQx bit to request that a scheduled message buffer (TXEx = 0) shall be aborted.
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Programmer’s Model of Control Registers IDAM1 and IDAM0— Identifier Acceptance Mode Flags The CPU sets these flags to define the identifier acceptance filter organization. See 16.4 Identifier Acceptance Filter. Table 16-8 summarizes the different settings. In filter closed mode, no messages are accepted so that the foreground buffer is never reloaded. Table 16-9.
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msCAN12 Controller 16.12.11 msCAN12 Transmit Error Counter Address: $010F Read: Bit 7 6 5 4 3 2 1 Bit 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 16-26. msCAN12 Transmit Error Counter (CTXERR) This register reflects the status of the msCAN12 transmit error counter. The register is read only. NOTE Both error counters may be read only when in sleep or soft-reset mode. 16.12.
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Programmer’s Model of Control Registers Address: $0118 Bit 7 Read: AC7 Write: Reset: Address: $0119 Bit 7 Read: AC7 Write: Reset: Address: $011A Bit 7 Read: AC7 Write: Reset: Address: $011B Bit 7 Read: AC7 Write: Reset: 6 5 4 3 2 1 Bit 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Unaffected by reset 6 5 4 3 2 1 Bit 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Unaffected by reset 6 5 4 3 2 1 Bit 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Unaffected by reset 6 5 4 3 2 1 Bit 0 AC6 AC5 AC4 AC3 AC2 A
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msCAN12 Controller Address: $0114 Bit 7 Read: AM7 Write: Reset: Address: $0115 Bit 7 Read: AM7 Write: Reset: Address: $0116 Bit 7 Read: AM7 Write: Reset: Address: $0117 Bit 7 Read: AM7 Write: Reset: 6 5 4 3 2 1 Bit 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Unaffected by reset 6 5 4 3 2 1 Bit 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Unaffected by reset 6 5 4 3 2 1 Bit 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Unaffected by reset 6 5 4 3 2 1 Bit 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Unaffected b
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Programmer’s Model of Control Registers AM7–AM0 — Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match will be detected. The message will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not affect whether or not the message is accepted.
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msCAN12 Controller 16.12.16 msCAN12 Port CAN Data Direction Register Address: $013F Bit 7 Read: Write: Reset: 6 5 4 3 2 DDRCAN7 DDRCAN6 DDRCAN5 DDRCAN4 DDRCAN3 DDRCAN2 0 0 0 0 0 0 1 Bit 0 0 0 0 0 = Unimplemented Figure 16-33. msCAN12 Port CAN Data Direction Register (DDRCAN) DDRCAN7–DDRCAN2 — Data Direction Port CAN Bits 0 = Respective input/output (I/O) pin is configured for input. 1 = Respective I/O pin is configured for output. M68HC12B Family Data Sheet, Rev. 9.
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Chapter 17 Analog-to-Digital Converter (ATD) 17.1 Introduction The ATD is an 8-channel, 10-bit, multiplexed-input, successive-approximation, analog-to-digital converter, accurate to ± 2 least significant bit (LSB). It does not require external sample and hold circuits because of the type of charge redistribution technique used. The ATD converter timing is synchronized to the system P clock.
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Analog-to-Digital Converter (ATD) VRH VRL RC DAC ARRAY AND COMPARATOR VDDA VSSA SAR ATD0 ANALOG MUX AND SAMPLE BUFFER AMPLIFIER MODE AND TIMING CONTROL ATD1 ATD2 AN7/PAD7 AN6/PAD6 AN5/PAD5 AN4/PAD4 AN3/PAD3 AN2/PAD2 AN1/PAD1 AN0/PAD0 PORT AD DATA INPUT REGISTER ATD3 ATD4 ATD5 ATD6 ATD7 CLOCK SELECT/PRESCALE INTERNAL BUS Figure 17-1. ATD Block Diagram M68HC12B Family Data Sheet, Rev. 9.
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ATD Registers 17.3 ATD Registers This section describes the ATD registers. 17.3.1 ATD Control Register 0 Address: $0060 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 17-2. ATD Control Register 0 (ATDCTL0) Read: Anytime Write: Anytime NOTE Writes to this register abort the current conversion sequence. 17.3.
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Analog-to-Digital Converter (ATD) ADPU — ATD Disable Bit Software can disable the clock signal to the ATD and power down the analog circuits to reduce power consumption. When reset to 0, the ADPU bit aborts any conversion sequence in progress. Because the bias currents to the analog circuits are turned off, the ATD requires a period of recovery time to stabilize the analog circuits after setting the ADPU bit.
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ATD Registers FRZ1 and FRZ0 — Background Debug (Freeze) Enable Bits When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint is encountered. These two bits determine how the ATD will respond when background debug mode becomes active. See Table 17-1. Table 17-1.
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Analog-to-Digital Converter (ATD) Clearing these bits causes the prescale value to default to 1 which results in a divide-by-two prescale factor. This signal is then fed into the divide-by-two logic. The reset state divides the P clock by a total of four and is appropriate for nominal operation at a bus rate of between 2 MHz and 8 MHz. Table 17-3 shows the divide-by operation and the appropriate range of system clock frequencies. Table 17-3.
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ATD Registers SCAN — Enable Continuous Channel Scan Bit When a conversion sequence is initiated by a write to the ATDCTL register, the user has a choice of performing a sequence of four (or eight, depending on the S8CM bit) conversions or continuously performing four (or eight) conversion sequences.
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Analog-to-Digital Converter (ATD) Table 17-4. Multichannel Mode Result Register Assignment (Continued) (Continued) S8CM 1 CD 1 CC CB CA Channel Signal Result in ADRx if MULT = 1 0 0 0 Reserved ADR0 0 0 1 Reserved ADR1 0 1 0 Reserved ADR2 0 1 1 Reserved ADR3 1 0 0 VRH ADR4 1 0 1 VRL ADR5 1 1 0 (VRH + VRL)/2 ADR6 1 1 1 Test/reserved ADR7 Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight channels makes up a conversion sequence.
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ATD Registers CC2–CC0 — Conversion Counter Bits for Current 4 or 8 Conversions This 3-bit value reflects the contents of the conversion counter pointer in a four or eight count sequence. This value also reflects which result register is written next, indicating which channel is currently being converted. CCF7–CCF0 — Conversion Complete Flags Each CCF bit is associated with an individual ATD result register.
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Analog-to-Digital Converter (ATD) 17.3.9 Port AD Data Input Register Address: $006F Read: Bit 7 6 5 4 3 2 1 Bit 0 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 Write: Reset: After reset, reflect the state of the inputs pins = Unimplemented Figure 17-12. Port AD Data Input Register (PORTAD) Read: Anytime Write: Has no meaning or effect PAD7–PAD0 — Port AD Data Input Bits After reset, these bits reflect the state of the input pins. PAD7–PAD0 may be used for general-purpose digital input.
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ATD Mode Operation Read: Anytime Write: Has no meaning or effect ADRxH[15:8]–ADRxH[7:0] — ATD Conversion Result Bits The reset condition for these registers is undefined. These bits contain the left-justified, unsigned result from the ATD conversion. The channel from which this result was obtained is dependant on the conversion mode selected. These registers are always read-only in normal mode. 17.4 ATD Mode Operation Stop Causes all clocks to halt (if the S bit in the CCR is 0).
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Analog-to-Digital Converter (ATD) ; ---------------------------------------------------------------------; MAIN PROGRAM ; ---------------------------------------------------------------------ORG $7000 ; 16K On-Board RAM, User code data area, start main program at $7000 INIT CONVERT DONE ; Branch to INIT subroutine to Initialize ATD ; Branch to CONVERT Subroutine for conversion ; Branch to Self, Convenient place for ; MAIN: BSR BSR DONE: BRA breakpoint ; ---------------------------------------------;
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Chapter 18 Development Support 18.1 Introduction Development support involves complex interactions between MCU resources and external development systems. This section concerns instruction queue and queue tracking signals, background debug mode, breakpoints, and instruction tagging. 18.2 Instruction Queue It is possible to monitor CPU activity on a cycle-by-cycle basis for debugging.
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Development Support Program information is fetched a few cycles before it is used by the CPU. To monitor cycle-by-cycle CPU activity, it is necessary to externally reconstruct what is happening in the instruction queue. Internally, the MCU only needs to buffer the data from program fetches. For system debug it is necessary to keep the data and its associated address in the reconstructed instruction queue.
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Background Debug Mode (BDM) Figure 18-1 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target M68HC12 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target E cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges.
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Development Support Figure 18-3 shows the host receiving a logic 0 from the target MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target MCU finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge.
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Background Debug Mode (BDM) 18.3.3 BDM Commands All BDM command opcodes are eight bits long and can be followed by an address and/or data, as indicated by the instruction. These commands do not require the CPU to be in active BDM for execution. The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle.
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Development Support Table 18-2. BDM Hardware Commands (Continued) Command Opcode (Hex) Data 16-bit address 16-bit data in WRITE_BD_WORD CC WRITE_BYTE C0 16-bit address 16-bit data in WRITE_WORD C8 16-bit address 16-bit data in Description Write to memory with BDM in map (may steal cycles if external access) must be aligned access. Write to memory with BDM out of map (may steal cycles if external access) data for odd address on low byte, data for even address on high byte.
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Background Debug Mode (BDM) The external host should wait 150 E-clock cycles for a non-intrusive BDM command to execute before another command is sent. This delay includes 128 E-clock cycles for the maximum delay for a free cycle. For data read commands, the host must insert this delay between sending the address and attempting to read the data. In the case of a write command, the host must delay after the data portion, before sending a new command, to be sure the write has finished.
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Development Support 18.3.5 BDM Instruction Register This section describes the BDM instruction register under hardware command and firmware command. 18.3.5.1 Hardware Command Address: $FF00 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 H/F DATA R/W BKGND W/B BD/U 0 0 0 0 0 0 0 0 0 0 Figure 18-4. BDM Instruction Register (INSTRUCTION) The bits in the BDM instruction register have the following meanings when a hardware command is executed.
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Background Debug Mode (BDM) 18.3.5.2 Firmware Command Address: $FF00 Read: Write: Reset: Bit 7 6 5 H/F DATA R/W 0 0 0 4 3 2 TTAGO 0 1 Bit 0 REGN 0 0 0 0 Figure 18-5. BDM Instruction Register (INSTRUCTION) The bits in the BDM instruction register have these meanings when a firmware command is executed.
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Development Support 18.3.6 BDM Status Register Address: $FF01 Bit 7 6 5 4 3 2 1 Bit 0 ENBDM EDMACT ENTAG SDV TRACE 0 0 0 Reset: 0 0 0 0 0 0 0 0 Single-Chip Peripheral: 1 0 0 0 0 0 0 0 Read: Write: Figure 18-6. BDM Status Register (STATUS) This register can be read or written by BDM commands or firmware. ENBDM — Enable BDM Bit (permit active background debug mode) 0 = BDM cannot be made active (hardware commands still allowed).
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Breakpoints 18.3.8 BDM Address Register Address: $FF04 Bit 7 6 5 4 3 2 1 Bit 0 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 Read: Write: Reset: Address: $FF05 Read: Write: Reset: Figure 18-8. BDM Address Register (ADDRESS) The 16-bit ADDRESS register is temporary storage for BDM hardware and firmware commands. The register can be read in all modes but is not normally accessed by users.
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Development Support 18.4.1 Breakpoint Modes Three modes of operation determine the type of breakpoint in effect. 1. Dual address-only breakpoints, each of which causes a software interrupt (SWI) 2. Single full-feature breakpoint which causes the part to enter background debug mode (BDM) 3. Dual address-only breakpoints, each of which causes the part to enter BDM Breakpoints do not occur when BDM is active. 18.4.1.
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Breakpoints 18.4.2 Breakpoint Registers Breakpoint operation consists of comparing data in the breakpoint address registers (BRKAH/BRKAL) to the address bus and comparing data in the breakpoint data registers (BRKDH/BRKDL) to the data bus. The breakpoint data registers also can be compared to the address bus. The scope of comparison can be expanded by ignoring the least significant byte of address or data matches.
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Development Support BK0ALE — Breakpoint 0 Range Control Bit Valid in all modes 0 = BRKAL is not used to compare to the address bus. 1 = BRKAL is used to compare to the address bus. Table 18-8. Breakpoint Address Range Control BK1ALE BK0ALE Address Range Selected — 0 Upper 8-bit address only for full mode or dual mode BKP0 — 1 Full 16-bit address for full mode or dual mode BKP0 0 — Upper 8-bit address only for dual mode BKP1 1 — Full 16-bit address for dual mode BKP1 18.4.2.
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Breakpoints BK1RW — R/W Compare Value Bit When BK1RWE = 1, this bit determines the type of bus cycle to match. 0 = A write cycle is matched. 1 = A read cycle is matched. BK0RWE — R/W Compare Enable Bit Enables the comparison of the R/W signal to further specify what causes a match. This bit is not useful in program breakpoints. 0 = R/W is not used in the comparisons. 1 = R/W is used in comparisons. BK0RW — R/W Compare Value Bit When BK0RWE = 1, this bit determines the type of bus cycle to match.
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Development Support 18.4.2.5 Breakpoint Data Register High Address: $0024 Read: Write: Power on reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Figure 18-14. Breakpoint Data Register High (BRKDH) These bits are compared to the most significant byte of the data bus in full breakpoint mode or the most significant byte of the address bus in dual address modes. BKE1, BKE0, BKDBE, and BKMBH control how this byte is used in the breakpoint comparison. 18.4.2.
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Instruction Tagging Table 18-10 shows the functions of the two tagging pins. The pins operate independently; the state of one pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall of ECLK performs the indicated function. Tagging is allowed in all modes. Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active. Table 18-10.
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Development Support M68HC12B Family Data Sheet, Rev. 9.
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Chapter 19 Electrical Specifications 19.1 Introduction This section contains electrical and timing specifications. 19.2 Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 19.5 5.0 Volt DC Electrical Characteristics for guaranteed operating conditions. Rating Symbol Value Unit VDD, VDDA, VDDX –0.3 to +6.
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Electrical Specifications 19.3 Functional Operating Range Rating Symbol Value Unit TA TL to TH −40 to +85 −40 to +105 −40 to +125 °C VDD 5.0 ± 10% V Symbol Value Unit Average junction temperature TJ TA + (PD × ΘJA) °C Ambient temperature TA User-determined °C ΘJA 76 °C/W All devices in this document meet these operating temperature ranges: “C” temperature range “V” temperature range “M” temperature range Operating voltage range 19.
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5.0 Volt DC Electrical Characteristics 19.5 5.0 Volt DC Electrical Characteristics Characteristic(1) Symbol Min Max Unit Input high voltage, all inputs VIH 0.7 × VDD VDD + 0.3 V Input low voltage, all inputs VIL VSS − 0.3 0.2 × VDD V Output high voltage, all I/O and output pins except XTAL Normal drive strength IOH = −10.0 µA IOH = −0.8 mA Reduced drive strength IOH = −4.0 µA IOH = −0.3 mA VOH VDD − 0.2 VDD − 0.8 — — V VDD − 0.2 VDD − 0.8 — — — — VSS + 0.2 VSS + 0.4 — — VSS + 0.
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Electrical Specifications 19.6 Supply Current Characteristic(1) Symbol Maximum total supply current RUN: Single-chip mode Expanded mode IDD 2 MHz 4 MHz 8 MHz Unit 15 25 25 45 45 70 mA mA WAIT: (All peripheral functions shut down) Single-chip mode Expanded mode WIDD 1.
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ATD DC Electrical Characteristics 19.8 ATD DC Electrical Characteristics Characteristic(1) Symbol Min Max Unit Analog supply voltage VDDA 4.5 5.5 V Analog supply current, normal operation IDDA — 1.0 mA Reference voltage, low VRL VSSA VDDA/2 V Reference voltage, high VRH VDDA/2 VDDA V VRH−VRL 4.5 5.
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Electrical Specifications 19.9 Analog Converter Operating Characteristics Characteristic(1) Symbol Min Typ Max Unit 1 count — 20 — mV 8-bit differential non-linearity(3) DNL −0.5 — +0.
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ATD AC Operating Characteristics (Operating) 19.10 ATD AC Operating Characteristics (Operating) Characteristic(1) Symbol Min Max Unit MCU clock frequency (p-clock) fPCLK 2.0 8.0 MHz ATD operating clock frequency fATDCLK 0.5 2.0 MHz ATD 8-bit conversion period ATD clock cycles(2) ATD conversion time(3) nCONV8 tCONV8 18 9 32 16 Cycles µs ATD 10-bit conversion period ATD clock cycles(2) ATD conversion time(3) nCONV10 tCONV10 20 10.
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Electrical Specifications 19.12 FLASH EEPROM Characteristics Characteristic(1) Symbol Min Typ Max Units Program/erase supply voltage Read only Program/erase/verify VFP VDD −0.35 11.4 VDD 12.0 VDD +0.5 12.
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FLASH EEPROM Characteristics 19.12.1 Programming Voltage Supply Envelope The key to preventing damage to the FLASH array or corruption of the data contained in the memory is the programming voltage envelope shown in Figure 19-1. Many of the problems that customers experience with FLASH devices are due to a failure to ensure that their voltage sources always meet these requirements.
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Electrical Specifications 19.12.2 Example VFP Protection Circuitry Figure 19-2 shows an example of a circuit which, if properly implemented, can maintain the appropriate voltage levels on the VFP pin. This section outlines the design for this circuit, what each component is intended to do, and some design considerations when designing VFP pin protection.
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FLASH EEPROM Characteristics NOTE Figure 19-2 is different from the recommended circuit shown in information about ST662A from ST Microelectronics, but it is correct. The change is in the location of the capacitor C4, which is now placed between VDD and VFP. This change was implemented with the cooperation of ST Microelectronics to aid in tracking a rapidly falling VDD voltage level, such as in Figure 19-3 and Figure 19-4.
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Electrical Specifications Figure 19-4. VFP Tracking VDD during Power-Down When checking to ensure that the reservoir capacitance value of C4 is not too low, the voltage level of VFP can be monitored during an initial erase and a write pulse. Remember that the largest current draw on erasing is when all of the bits of the FLASH are programmed to 0. Conversely, the highest programming current is seen when programming all the bits to 0 from the erased state of 1.
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Pulse-Width Modulator Characteristics 19.13 Pulse-Width Modulator Characteristics Characteristic(1) Symbol Min Max Unit E-clock frequency fECLK — 8.
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Electrical Specifications 19.14 Control Timing 8.0 MHz Characteristic Symbol Unit Min Max fo dc 8.0 MHz tcyc 125 — ns fXTAL — 16.0 MHz External oscillator frequency 2 fo dc 16.
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Freescale Semiconductor VDD M68HC12B Family Data Sheet, Rev. 9.1 EXTAL 4098 tcyc ECLK tPCSU PWRSTL RESET tMPH tMPS MODA, MODB INTERNAL ADDRESS FFFE FFFE FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC FFFE FFFE FFFE FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Note: Reset timing is subject to change. Figure 19-6.
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Electrical Specifications 322 INTERNAL CLOCKS IRQ(1) M68HC12B Family Data Sheet, Rev. 9.1 PWIRQ IRQ(2) or XIRQ tSTOPDELAY(3) ECLK ADDRESS(4) SP-6 SP-8 SP-9 FREE FREE OPT FETCH 1ST EXEC Resume program with instruction which follows the STOP instruction. ADDRESS(5) SP-6 SP-8 SP-9 FREE VECTOR FREE 1ST PIPE Notes: 1. Edge-sensitive IRQ pin (IRQE bit = 1) 2. Level-sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 tcyc if DLY = 0. 4. XIRQ with X bit in CCR = 1. 5.
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Freescale Semiconductor ECLK M68HC12B Family Data Sheet, Rev. 9.1 tPCSU IRQ, XIRQ, OR INTERNAL INTERRUPTS tWRS ADDRESS SP – 2 SP – 4 SP – 6 . . . SP – 9 SP – 9 SP – 9 . . . SP – 9 SP – 9 VECTOR ADDRESS FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC PC, IY, IX, B:A, CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. Figure 19-8.
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Electrical Specifications 324 ECLK M68HC12B Family Data Sheet, Rev. 9.1 tPCSU IRQ, XIRQ, OR INTERNAL INTERRUPTS tWRS ADDRESS SP – 2 SP – 4 SP – 6 . . . SP – 9 SP – 9 SP – 9 . . . SP – 9 SP – 9 PC, IY, IX, B:A, CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. Figure 19-9.
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Peripheral Port Timing 19.15 Peripheral Port Timing 8.0 MHz Characteristic Symbol Unit Min Max fo dc 8.
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Electrical Specifications 19.16 Multiplexed Expansion Bus Timing NOTE Use of the multiplexed expansion bus at 8 MHz is discouraged due to TAD delay factors. Num Characteristic(1), (2), (3), (4), (5) Delay Symbol 8 MHz 2 MHz Min Max Min Max Unit — Frequency of operation (E-clock frequency) — fo dc 8.0 dc 8.
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Multiplexed Expansion Bus Timing 1 2 3 ECLK 16 17 18 19 20 21 R/W LSTRB W/O TAG ENABLED 5 READ 23 7 12 ADDRESS ADDRESS/DATA MULTIPLEXED DATA 9 8 13 WRITE 11 22 10 ADDRESS 15 14 DATA 24 25 26 DBE Note: Measurement points shown are 20% and 70% of VDD. Figure 19-12. Multiplexed Expansion Bus Timing Diagram M68HC12B Family Data Sheet, Rev. 9.
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Electrical Specifications 19.
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Serial Peripheral Interface (SPI) Timing SS(1) OUTPUT 5 2 1 SCK CPOL = 0) OUTPUT 3 12 4 4 13 SCK CPOL = 1 OUTPUT 6 7 MISO INPUT MSB IN(2) BIT 6 . 10 . . 1 LSB IN 10 MOSI OUTPUT MSB OUT(2) 11 BIT 6 . . . 1 LSB OUT Notes: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. A) SPI Master Timing (CPHA = 0) SS(1) OUTPUT 5 1 2 13 12 12 13 3 SCK CPOL = 0 OUTPUT 4 4 SCK CPOL = 1 OUTPUT 6 MISO INPUT 7 MSB IN(2) BIT 6 .
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Electrical Specifications SS INPUT 5 1 13 12 12 13 3 SCK CPOL = 0 INPUT 4 2 4 SCK CPOL = 1 INPUT 9 8 MISO OUTPUT 10 BIT 6 . MSB OUT SLAVE 6 11 11 . . 1 SLAVE LSB OUT SEE NOTE 7 MOSI INPUT BIT 6 . MSB IN . . 1 LSB IN Note: Not defined but normally MSB of character just received A) SPI Slave Timing (CPHA = 0) SS INPUT 5 3 1 2 13 12 12 13 SCK CPOL = 0 INPUT 4 4 SCK CPOL = 1 INPUT SEE NOTE 8 MOSI INPUT 9 11 10 MISO OUTPUT SLAVE MSB OUT 6 BIT 6 . . .
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Chapter 20 Mechanical Specifications 20.1 Introduction This section provides dimensions for the 80-pin quad flat pack (QFP). M68HC12B Family Data Sheet, Rev. 9.
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Mechanical Specifications 20.2 80-Pin Quad Flat Pack (Case 841B-02) L 60 41 61 B B S V P B 0.20 M C A-B L 0.05 A-B -B- -A- 0.20 M H A-B S D D S S 40 -A-,-B-,-DDETAIL A DETAIL A 21 80 1 A 0.20 M H A-B S F 20 -DD S 0.05 A-B J S 0.20 M C A-B S D S D M E DETAIL C C -H- -CSEATING PLANE N DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H M G U T -H- R DATUM PLANE K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.
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How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. E-mail: support@freescale.com For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp.