Datasheet

Clock Generation Module (CGM)
M68HC12B Family Data Sheet, Rev. 9.1
114 Freescale Semiconductor
10.3 Register Map
10.4 Clock Selection and Generation
The CGM generates the P clock, the E clock, and four T clocks. The P clock and E clock are used by all
device modules except the CPU. The T clocks are used by the CPU.
Figure 10-3 shows clock timing relationships while in normal run modes.
There are two types of P clocks and E clocks while in wait mode:
• Global type (G), which is driven by the slow clock divider in wait mode and drives all on-chip
peripherals except the BDLC and the TIMER
• Global type (GBT), which remains at the oscillator divide-by-2 rate in wait mode and drives the
BDLC and the TIMER
Figure 10-4 shows clock timing relationships while in wait mode.
Addr. Register Name Bit 7654321Bit 0
$0014
Real-Time Interrupt Control
Register (RTICTL)
See page 118.
Read:
RTIE RSWAI RSBCK
0
RTBYP RTR2 RTR1 RTR0
Write:
Reset:00000000
$0015
Real-Time Interrupt Flag Register
(RTIFLG)
See page 119.
Read:
RTIF0000000
Write:
Reset:00000000
$0016
COP Control Register (COPCTL)
See page 119.
Read:
CME FCME FCM FCOP DISR CR2 CR1 CR0
Write:
Reset:00000001
$0017
Arm/Reset COP Timer
Register (COPRST)
See page 120.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
$00E0
Slow Mode Divider Register
(SLOW)
See page 117.
Read: 0 0 0 0 0
SLDV2 SLDV1 SLDV0
Write:
Reset:00000000
= Unimplemented
Figure 10-2. CGM Register Map