Datasheet

Clock Selection and Generation
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 115
Figure 10-3. Internal Clock Relationships in Normal Run Modes
Figure 10-4. Internal Clock Relationships in Wait Mode
T1 CLOCK
T2 CLOCK
T3 CLOCK
T4 CLOCK
E CLOCK
P CLOCK
OSCILLATOR
E CLOCK
P CLOCK
OSCILLATOR
T1 CLOCK
T2 CLOCK
T3 CLOCK
T4 CLOCK
E CLOCK
P CLOCK
1. Driven by slow clock divider in wait mode. Drives on-chip peripherals except BDLC and timer.
2. Remains at oscillator divided by 2 rate in wait mode. Drives BDLC and timer.
Notes:
(G)
(1)
(G)
(1)
(GBT)
(2)
(GBT)
(2)