Datasheet

Clock Generation Module (CGM)
M68HC12B Family Data Sheet, Rev. 9.1
118 Freescale Semiconductor
10.7.2 Real-Time Interrupt Control Register
Read: Anytime
Write: Varies on a bit-by-bit basis
RTIE — Real-Time Interrupt Enable Bit
Write anytime.
0 = Interrupt requests from RTI are disabled.
1 = Interrupt is requested when RTI is set.
RSWAI — RTI and COP Stop While in Wait Bit
Write once in normal modes, anytime in special modes.
0 = Allows the RTI and COP to continue running in wait
1 = Disables both the RTI and COP when the part goes into wait
RSBCK — RTI and COP Stop While in Background Debug Mode Bit
Write once in normal modes, anytime in special modes.
0 = Allows the RTI and COP to continue running while in background mode
1 = Disables RTI and COP when the part is in background mode (useful for emulation)
RTBYP — Real-Time Interrupt Divider Chain Bypass Bit
Write is not allowed in normal modes, anytime in special modes.
0 = Divider chain functions normally.
1 = Divider chain is bypassed, allows faster testing. The divider chain is normally P divided by 2
13
,
when bypass becomes P divided by 4.
RTR2, RTR1, and RTR0 — Real-Time Interrupt Rate Select Bits
Write anytime.
Rate select for real-time interrupt. The E clock is used for this module.
Address: $0014
Bit 7654321Bit 0
Read:
RTIE RSWAI RSBCK
0
RTBYP RTR2 RTR1 RTR0
Write:
Reset:00000000
= Unimplemented
Figure 10-6. Real-Time Interrupt Control Register (RTICTL)
Table 10-3. Real-Time Interrupt Rates
RTR2 RTR1 RTR0 Divide E By:
Timeout Period
E = 4.0 MHz
Timeout Period
E = 8.0 MHz
000 OFF OFF OFF
001
2
13
2.048 ms 1.024 ms
010
2
14
4.096 ms 2.048 ms
011
2
15
8.196 ms 4.096 ms
100
2
16
16.384 ms 8.196 ms
101
2
17
32.768 ms 16.384 ms
110
2
18
65.536 ms 32.768 ms
111
2
19
131.72 ms 65.536 ms