Datasheet

Clock Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 119
10.7.3 Real-Time Interrupt Flag Register
RTIF — Real-Time Interrupt Flag Bit
This bit is cleared automatically by a write to this register with this bit set.
0 = Timeout has not yet occurred.
1 = Set when the timeout period is met
10.7.4 COP Control Register
Read: Anytime
Write: Varies on a bit by bit basis
CME — Clock Monitor Enable Bit
Write anytime.
If FCME is set, this bit has no meaning or effect.
0 = Clock monitor is disabled; slow clocks and STOP instruction may be used.
1 = Slow or stopped clocks (including the STOP instruction) cause a clock reset sequence.
FCME — Force Clock Monitor Enable Bit
Write once in normal modes, anytime in special modes.
In normal modes, when this bit is set, the clock monitor function cannot be disabled until a reset occurs.
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks cause a clock reset sequence.
To use both STOP and clock monitor, the CME bit should be cleared prior to executing a STOP
instruction and set after recovery from STOP. Always keep FCME = 0, if STOP will be used.
FCM — Force Clock Monitor Reset Bit
Writes are not allowed in normal modes, anytime in special modes.
If DISR is set, this bit has no effect.
0 = Normal operation
1 = Force a clock monitor reset, if clock monitor is enabled.
Address: $0015
Bit 7654321Bit 0
Read:
RTIF0000000
Write:
Reset:00000000
Figure 10-7. Real-Time Interrupt Flag Register (RTIFLG)
Address: $0016
Bit 7654321Bit 0
Read:
CME FCME FCM FCOP DISR CR2 CR1 CR0
Write:
Normal Reset:00000001
Special Reset:00001001
Figure 10-8. COP Control Register (COPCTL)