Datasheet

Clock Generation Module (CGM)
M68HC12B Family Data Sheet, Rev. 9.1
120 Freescale Semiconductor
FCOP — Force COP Watchdog Reset Bit
Writes are not allowed in normal modes; can be written anytime in special modes.
If DISR is set, this bit has no effect.
0 = Normal operation
1 = Force a COP reset, if COP is enabled.
DISR — Disable Resets from COP Watchdog and Clock Monitor Bit
Writes are not allowed in normal modes, anytime in special modes.
0 = Normal operation
1 = Regardless of other control bit states, COP and clock monitor do not generate a system reset.
CR2, CR1, and CR0 — COP Watchdog Timer Rate Select Bit
The COP system is driven by a constant frequency of E/2
13
. (RTBYP in the RTICTL register allows all
but two stages of this divider to be bypassed for testing in special modes only.) These bits specify an
additional division factor to arrive at the COP timeout rate. The clock used for this module is the E
clock.
Write once in normal modes, anytime in special modes.
10.7.5 Arm/Reset COP Timer Register
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog sequence.
Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may
be executed between these writes but both must be completed in the correct order prior to timeout to
avoid a watchdog reset. Writing anything other than $55 or $AA causes a COP reset to occur.
Table 10-4. COP Watchdog Rates (RTBYP = 0)
CR2 CR1 CR0 Divide E By:
At E = 4.0-MHz
Timeout
0 to +2.048 ms
At E = 8.0-MHz
Timeout
0 to +1.024 ms
0 0 0 OFF OFF OFF
001
2
13
2.048 ms 1.024 ms
010
2
15
8.1920 ms 4.096 ms
011
2
17
32.768 ms 16.384 ms
100
2
19
131.072 ms 65.536 ms
101
2
21
524.288 ms 262.144 ms
110
2
22
1.048 s 524.288 ms
111
2
23
2.097 s 1.048576 s
Address: $0017
Bit 7654321Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
Figure 10-9. Arm/Reset COP Timer Register (COPRST)