Datasheet

Clock Divider Chains
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 121
10.8 Clock Divider Chains
Figure 10-10, Figure 10-11, Figure 10-12, and Figure 10-13 summarize the clock divider chains for these
peripherals:
• SCI — Serial peripheral interface
• BDLC — Byte data link communications
• RTI — Real-time interrupt
• COP — Computer operating properly
• TIM — Standard timer module
• ECT — Enhanced capture timer
• SPI — Serial peripheral interface
• ATD — Analog-to-digital converter
• BDM — Background debug mode
Figure 10-10. Clock Chain for SCI, BDLC, RTI, and COP
P CLOCK
BITS: RTR2, RTR1, AND RTR0
BITS: CR2, CR1, AND CR0
÷ 2
4
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 4
÷ 4
÷ 4
÷ 2
÷ 4
÷ 2
REGISTER: COPCTLREGISTER: RTICTL
÷ 2
11
÷ 2
2
BIT: RTBYP
REGISTER: RTICTL
0:0
0:1
1:0
1:1
÷ 2
÷ 2
÷ 2
BITS: R1, R0
REGISTER: BCR1
TO BDLC TO RTI TO COP
SC0BD
MODULUS DIVIDER:
÷ 1, 2, 3, 4, 5, 6, ..., 8190, 8191
SCI0
RECEIVE
BAUD RATE (16x)
SCI0
TRANSMIT
BAUD RATE (1x)