Datasheet

Pulse-Width Modulator (PWM)
M68HC12B Family Data Sheet, Rev. 9.1
126 Freescale Semiconductor
Figure 11-1. Block Diagram of PWM Left-Aligned Output Channel
Figure 11-2. Block Diagram of PWM Center-Aligned Output Channel
GATE
PWCNTx
8-BIT COMPARE
PWDTYx
8-BIT COMPARE =
PWPERx
UP
COUNTER ONLY
FROM PORT P
DATA REGISTER
TO PIN
DRIVER
PPOLx
CLOCK SOURCE
(ECLK)
CLOCK EDGE SYNC RESET
CENTR = 0
MUX
MUX
S
R
Q
Q
PWPER
PWDTY
PWENx
PPOL = 0
PPOL = 1
GATE
PWCNTx
8-BIT COMPARE
PWDTYx
8-BIT COMPARE =
PWPERx
RESET
FROM PORT P
DATA REGISTER
TO PIN
DRIVER
PPOLx
CLOCK SOURCE
(ECLK)
CLOCK EDGE SYNC
CENTR = 1
MUX
MUX
T
Q
Q
PWDTY
PWENx
PPOL = 0
PPOL = 1
DUTY CYCLE
PERIOD
PWPER
× 2
(PWPER − PWDTY) × 2
PWDTY
UP/DOWN COUNTER
WITH RESET UPON ENABLE