Datasheet

Pulse-Width Modulator (PWM)
M68HC12B Family Data Sheet, Rev. 9.1
128 Freescale Semiconductor
11.2 PWM Register Descriptions
This section provides descriptions of the PWM registers.
11.2.1 PWM Clocks and Concatenate Register
Read: Anytime
Write: Anytime
CON23 — Concatenate PWM Channels 2 and 3 Bit
When concatenated, channel 2 becomes the high-order byte and channel 3 becomes the low-order
byte. Channel 2 output pin is used as the output for this 16-bit PWM (bit 2 of port P). Channel 3
clock-select control bits determines the clock source.
0 = Channels 2 and 3 are separate 8-bit PWMs.
1 = Channels 2 and 3 are concatenated to create one 16-bit PWM channel.
CON01 — Concatenate PWM Channels 0 and 1 Bit
When concatenated, channel 0 becomes the high-order byte and channel 1 becomes the low-order
byte. Channel 0 output pin is used as the output for this 16-bit PWM (bit 0 of port P). Channel 1
clock-select control bits determine the clock source.
0 = Channels 0 and 1 are separate 8-bit PWMs.
1 = Channels 0 and 1 are concatenated to create one 16-bit PWM channel.
PCKA2–PCKA0 — Prescaler for Clock A Bits
Clock A is one of two clock sources which may be used for channels 0 and 1. These three bits
determine the rate of clock A, as shown in Table 11-1.
PCKB2–PCKB0 — Prescaler for Clock B Bits
Clock B is one of two clock sources which may be used for channels 2 and 3. These three bits
determine the rate of clock B, as shown in Table 11-1.
Address: $0040
Bit 7654321Bit 0
Read:
CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0
Write:
Reset:00000000
Figure 11-4. PWM Clocks and Concatenate Register (PWCLK)
Table 11-1. Clock A and Clock B Prescaler
PCKA2 (PCKB2) PCKA1 (PCKB1) PCKA0 (PCKB0) Value of Clock A (B)
000 E
001 E ÷ 2
010 E ÷ 4
011 E ÷ 8
100E ÷ 16
101E ÷ 32
110E ÷ 64
111E ÷ 128