Datasheet

Pulse-Width Modulator (PWM)
M68HC12B Family Data Sheet, Rev. 9.1
136 Freescale Semiconductor
11.2.12 PWM Control Register
Read: Anytime
Write: Anytime
PSWAI — PWM Halts While in Wait Mode Bit
0 = Continue PWM main clock generator while in wait mode.
1 = Halt PWM main clock generator when the part is in wait mode.
CENTR — Center-Aligned Output Mode Bit
To avoid irregularities in the PWM output mode, write the CENTR bit only when PWM channels are
disabled.
0 = PWM channels operate in left-aligned output mode.
1 = PWM channels operate in center-aligned output mode.
RDPP — Reduced Drive of Port P Bit
0 = Full drive for all port P output pins
1 = Reduced drive for all port P output pins
PUPP — Pullup Port P Enable Bit
0 = Disable port P pullups
1 = Enable pullups for all port P input pins.
PSBCK — PWM Stops While in Background Mode Bit
0 = Allows PWM to continue while in background mode
1 = Disable PWM input clock while in background mode.
Address: $0054
Bit 7654321Bit 0
Read: 0 0 0
PSWAI CENTR RDPP PUPP PSBCK
Write:
Reset:00000000
= Unimplemented
Figure 11-24. PWM Control Register (PWCTL)