Datasheet

M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 141
Chapter 12
Standard Timer (TIM)
12.1 Introduction
The standard timer module (TIM) for the MC68HC912B32 and MC68HC(9)12BC32 consists of a 16-bit
software-programmable counter driven by a prescaler. It contains eight complete 16-bit input
capture/output compare channels and one 16-bit pulse accumulator. See Figure 12-2.
The MC68HC12BE32 contains an enhanced capture timer (ECT). The timer on the MC68HC12BE32 is
backward compatible with code used on the MC68HC912B32. See Chapter 13 Enhanced Capture Timer
(ECT) Module for technical information on this timer.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from less than a microsecond to many seconds.
It can also generate pulse-width modulator (PWM) signals without CPU intervention.
12.2 Timer Registers
Input/output (I/O) pins default to general-purpose I/O lines until an internal function which uses that pin is
specifically enabled. The timer overrides the state of the DDR to force the I/O state of each associated
port line when an output compare using a port line is enabled. In these cases, the data direction bits will
have no effect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing to this PORTTn bit does not affect
the pin, but the data is stored in an internal latch such that if the pin becomes available for
general-purpose output the driven level will be the last value written to the PORTTn bit.
12.2.1 Timer Input Capture/Output Compare Select Register
Read: Anytime
Write: Anytime
IOS7–IOS0 —Input Capture or Output Compare Channel Designator Bits
0 = Corresponding channel acts as an input capture.
1 = Corresponding channel acts as an output compare.
Address: $0080
Bit 7654321Bit 0
Read:
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Write:
Reset:00000000
Figure 12-1. Timer Input Capture/Output Compare Select Register (TIOS)