Datasheet

Block Diagram
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 143
12.3.1 Timer Compare Force Register
Read: Anytime, always returns $00 (1 state is transient)
Write: Anytime
FOC7–FOC0 — Force Output Compare Action Bits for Channels 7–0
A write to this register with the corresponding data bit(s) set causes the action which is programmed
for output compare n to occur immediately. The action taken is the same as if a successful comparison
had just taken place with the TCn register except that the interrupt flag does not get set.
12.3.2 Output Compare 7 Mask Register
Read: Anytime
Write: Anytime
The bits of OC7M correspond bit-for-bit with the bits of the timer port (PORTT). Setting the OC7Mn sets
the corresponding port to be an output port regardless of the state of the DDRTn bit when the
corresponding TIOSn bit is set to be an output compare. This does not change the state of the DDRT bits.
12.3.3 Output Compare 7 Data Register
Read: Anytime
Write: Anytime
The bits of OC7D correspond bit-for-bit with the bits of the timer port (PORTT). When a successful OC7
compare occurs, for each bit that is set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
When the OC7Mn bit is set, a successful OC7 action will override a successful OC6–OC0 compare action
during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit.
Address: $0081
Bit 7654321Bit 0
Read:
FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Write:
Reset:00000000
Figure 12-3. Timer Compare Force Register (CFORC)
Address: $0082
Bit 7654321Bit 0
Read:
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Write:
Reset:00000000
Figure 12-4. Output Compare 7 Mask Register (OC7M)
Address: $0083
Bit 7654321Bit 0
Read:
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
Reset:00000000
Figure 12-5. Output Compare 7 Data Register (OC7D)