Datasheet

Block Diagram
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 145
TSBCK — Timer Stops While in Background Mode Bit
0 = Allows timer to continue running while in background mode
1 = Disables timer when MCU is in background mode; useful for emulation
TFFCA — Timer Fast Flag Clear All Bit
0 = Allows timer flag clearing to function normally
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel
($90–$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any
access to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register
($A2 and $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1).
This has the advantage of eliminating software overhead in a separate clear sequence.
NOTE
Extra care is required to avoid accidental flag clearing due to unintended
accesses.
12.3.6 Timer Control Registers
Read: Anytime
Write: Anytime
OMn — Output mode
OLn — Output level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare (see Table 12-1). When either OMn or OLn is 1, the pin associated with OCn
becomes an output tied to OCn regardless of the state of the associated DDRT bit.
Address: $0088
Bit 7654321Bit 0
Read:
OM7OL7OM6OL6OM5OL5OM4OL4
Write:
Reset:00000000
Figure 12-8. Timer Control Register 1 (TCTL1)
Address: $0089
Bit 7654321Bit 0
Read:
OM3OL3OM2OL2OM1OL1OM0OL0
Write:
Reset:00000000
Figure 12-9. Timer Control Register 2 (TCTL2)
Table 12-1. Compare Result Output Action
OMn OLn Action
0 0 Timer disconnected from output pin logic
0 1 Toggle OCn output line
1 0 Clear OCn output line to 0
1 1 Set OCn output line to 1