Datasheet

Standard Timer (TIM)
M68HC12B Family Data Sheet, Rev. 9.1
146 Freescale Semiconductor
Read: Anytime
Write: Anytime
EDGnB and EDGnA — Input Capture Edge Control Bits
These 8 pairs of control bits configure the input capture edge detector circuits. See Table 12-2.
12.3.7 Timer Interrupt Mask Registers
Read: Anytime
Write: Anytime
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the
corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled
to cause a hardware interrupt.
Address: $008A
Bit 7654321Bit 0
Read:
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write:
Reset:00000000
Figure 12-10. Timer Control Register 3 (TCTL3)
Address: $008B
Bit 7654321Bit 0
Read:
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Write:
Reset:00000000
Figure 12-11. Timer Control Register 4 (TCTL4)
Table 12-2. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)
Address: $008C
Bit 7654321Bit 0
Read:
C7I C6I C5I C4I C3I C2I C1I C0I
Write:
Reset:00000000
Figure 12-12. Timer Interrupt Mask 1 Register (TMSK1)