Datasheet

Standard Timer (TIM)
M68HC12B Family Data Sheet, Rev. 9.1
148 Freescale Semiconductor
12.3.8 Timer Interrupt Flag Registers
Read: Anytime
Write: Used in the clearing mechanism; set bits cause corresponding bits to
be cleared
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a 1 to
the bit. Writing a logic 0 does not affect current status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel ($90–$9F) causes the corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel n Flag
Read: Anytime
Write: Used in the clearing mechanism; set bits cause corresponding bits to
be cleared
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit to 1.
Any access to TCNT clears TFLG2 register, if the TFFCA bit in TSCR register is set.
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by
a write to the TFLG2 register with bit 7 set. For additional information, see the TCRE control bit
explanation found in 12.3.7 Timer Interrupt Mask Registers.
Address: $008E
Bit 7654321Bit 0
Read:
C7F C6F C5F C4F C3F C2F C1F C0F
Write:
Reset:00000000
Figure 12-14. Timer Interrupt Flag 1 (TFLG1)
Address: $008F
Bit 7654321Bit 0
Read:
TOF0000000
Write:
Reset:00000000
Figure 12-15. Timer Interrupt Flag 2 (TFLG2)