Datasheet

Block Diagram
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 153
12.3.11 Pulse Accumulator Flag Register
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register clears all the flags in
the PAFLG register.
PAOVF — Pulse Accumulator Overflow Flag
Set when the 16-bit pulse accumulator overflows from $FFFF to $0000. This bit is cleared
automatically by a write to the PAFLG register with bit 1 set.
PAIF — Pulse Accumulator Input Edge Flag
Set when the selected edge is detected at the pulse accumulator input pin. In event mode, the event
edge triggers PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the pulse
accumulator input pin triggers PAIF. This bit is cleared automatically by a write to the PAFLG register
with bit 0 set.
12.3.12 16-Bit Pulse Accumulator Count Register
Read: Anytime
Write: Anytime
Full count register access should take place in one clock cycle. A separate read/write for high byte and
low byte will give a different result than accessing them as a word.
Address: $00A1
Bit 7654321Bit 0
Read:
000000PAOVFPAIF
Write:
Reset:00000000
Figure 12-25. Pulse Accumulator Flag Register (PAFLG)
Address: $00A2
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Address: $00A3
Bit 7654321Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
Figure 12-26. 16-Bit Pulse Accumulator Count Register (PACNT)